[Intel-gfx] [PATCH v2 2/2] drm/i915: set HDMI pixel clock in audio configuration
David Härdeman
david at hardeman.nu
Thu Oct 24 11:59:35 CEST 2013
It should also be noted that manually hard-coding the pixel clock value
to an obviously incorrect value will also cause the Pioneer receiver to
do the right thing (I assume it will ignore the incorrect value and
calculate it on the fly) - that would point towards some kind of bug /
hardware incompatibility in the Pioneer receiver. But I agree that the
receiver *does* work with other hardware that I've tried.
Attempts to contact Pioneer have been fruitless so far. Maybe Intel
would have better luck there...
On 2013-10-24 11:07, Jasper Smet wrote:
> Although i know it also happens in windows, the one particular thing i
> am 'fiddling' with is that when i try the receiver with an nvidia or
> amd apu (ion, e-450 trough hdmi) with my pioneer receiver audio works
> fine with 44100hz at the 1080p at 50/60 modes. Only with intel i need to
> force upstreaming to 48000hz.
>
> So are we really sure this is a bug with the receiver or still
> something wrong with the driver / pixel clock issue?
>
> Is there anything else we i do to help ?
>
> On Wed, Oct 16, 2013 at 11:34 AM, Jani Nikula <jani.nikula at intel.com>
> wrote:
>
>> The HDMI audio expects HDMI pixel clock to be set in the audio
>> configuration. We've currently just set 0, using 25.2 / 1.001 kHz
>> frequency, which fails with some modes.
>>
>> v2: Now with a commit message.
>>
>> Reference:
>>
> http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
>> [1]
>> Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu
>> Reported-by: David Härdeman <david at hardeman.nu>
>> Reported-by: Jasper Smet <josbeir at gmail.com>
>> Tested-by: Jasper Smet <josbeir at gmail.com>
>> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++-
>> drivers/gpu/drm/i915/intel_display.c | 48
>> +++++++++++++++++++++++++++++++---
>> 2 files changed, 55 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 13153c3..3266819 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4875,7 +4875,17 @@
>> #define AUD_CONFIG_LOWER_N_SHIFT 4
>> #define AUD_CONFIG_LOWER_N_VALUE (0xfff <<
>> 4)
>> #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
>> -#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
>> +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
>> #define AUD_CONFIG_DISABLE_NCTS (1 << 3)
>>
>> /* HSW Audio */
>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>> b/drivers/gpu/drm/i915/intel_display.c
>> index 55740f2..a097f84 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6722,6 +6722,44 @@ static int intel_crtc_mode_set(struct
>> drm_crtc *crtc,
>> return 0;
>> }
>>
>> +static struct {
>> + int clock;
>> + u32 config;
>> +} hdmi_audio_clock[] = {
>> + { DIV_ROUND_UP(25200 * 1000, 1001),
>> AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
>> + { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default
>> per bspec */
>> + { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
>> + { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
>> },
>> + { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
>> + { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
>> },
>> + { DIV_ROUND_UP(74250 * 1000, 1001),
>> AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
>> + { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
>> + { DIV_ROUND_UP(148500 * 1000, 1001),
>> AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
>> + { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
>> +};
>> +
>> +/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
>> +static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode
>> *mode)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
>> + if (mode->clock ==
>> hdmi_audio_clock[i].clock)
>> + break;
>> + }
>> +
>> + if (i == ARRAY_SIZE(hdmi_audio_clock)) {
>> + DRM_DEBUG_KMS("HDMI audio pixel clock
>> setting for %d not found, falling back to defaultsn", mode->clock);
>> + i = 1;
>> + }
>> +
>> + DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d
>> (0x%08x)n",
>> + hdmi_audio_clock[i].clock,
>> + hdmi_audio_clock[i].config);
>> +
>> + return hdmi_audio_clock[i].config;
>> +}
>> +
>> static bool intel_eld_uptodate(struct drm_connector *connector,
>> int reg_eldv,
>> uint32_t bits_eldv,
>> int reg_elda,
>> uint32_t bits_elda,
>> @@ -6847,8 +6885,9 @@ static void haswell_write_eld(struct
>> drm_connector *connector,
>> DRM_DEBUG_DRIVER("ELD: DisplayPort
>> detectedn");
>> eld[5] |= (1 << 2); /* Conn_Type, 0x1
>> = DisplayPort */
>> I915_WRITE(aud_config,
>> AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
>> - } else
>> - I915_WRITE(aud_config, 0);
>> + } else {
>> + I915_WRITE(aud_config,
>> audio_config_hdmi_pixel_clock(mode));
>> + }
>>
>> if (intel_eld_uptodate(connector,
>> aud_cntrl_st2, eldv,
>> @@ -6926,8 +6965,9 @@ static void ironlake_write_eld(struct
>> drm_connector *connector,
>> DRM_DEBUG_DRIVER("ELD: DisplayPort
>> detectedn");
>> eld[5] |= (1 << 2); /* Conn_Type, 0x1
>> = DisplayPort */
>> I915_WRITE(aud_config,
>> AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
>> - } else
>> - I915_WRITE(aud_config, 0);
>> + } else {
>> + I915_WRITE(aud_config,
>> audio_config_hdmi_pixel_clock(mode));
>> + }
>>
>> if (intel_eld_uptodate(connector,
>> aud_cntrl_st2, eldv,
>> --
>> 1.7.9.5
>
> --
> Met Vriendelijke Groeten
>
> Jasper Smet
> Developer
>
> Twitter: josbeir
> E-mail: josbeir at gmail.com
> Mobile: 0486/41.75.45
>
> Links:
> ------
> [1]
> http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com
More information about the Intel-gfx
mailing list