[Intel-gfx] [PATCH 4/4] drm/i915: WaFbcDisableDpfcClockGating only with fbc

[Paulo Zanoni]

2013/10/24 Ben Widawsky <benjamin.widawsky at intel.com>:
> We were turning this on for SNB regardless of whether or not we use FBC.
> We can save the slightest amount of power if we don't disable it when
> not using FBC.
>
> The workaround should be bit 9 for SNB.

First, see comment in patch 3. So you're removing the WA on ILK and
applying it for SNB-only. Since the spec doesn't say "SNB only", I
guess we need this WA on both gens.

>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 25 +++++++++++++++----------
>  1 file changed, 15 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bbcf100..4ebbe65 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -237,6 +237,12 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
>                 I915_WRITE(SNB_DPFC_CTL_SA,
>                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
>                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
> +
> +               /* WaFbcDisableDpfcClockGating:snb */
> +               I915_WRITE(ILK_DSPCLK_GATE_D,
> +                          I915_READ(ILK_DSPCLK_GATE_D) |
> +                          ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
> +
>                 sandybridge_blit_fbc_update(dev);
>         } else {
>                 /* WaFbcDisableDpfcClockGating:ilk */
> @@ -259,7 +265,12 @@ static void ironlake_disable_fbc(struct drm_device *dev)
>                 dpfc_ctl &= ~DPFC_CTL_EN;
>                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
>
> -               if (IS_GEN5(dev))
> +               if (IS_GEN6(dev))
> +                       /* WaFbcDisableDpfcClockGating:snb */
> +                       I915_WRITE(ILK_DSPCLK_GATE_D,
> +                                  I915_READ(ILK_DSPCLK_GATE_D) &
> +                                  ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
> +               else if (IS_GEN5(dev))
>                         /* WaFbcDisableDpfcClockGating:ilk */
>                         I915_WRITE(ILK_DSPCLK_GATE_D,
>                                    I915_READ(ILK_DSPCLK_GATE_D) &
> @@ -4939,15 +4950,9 @@ static void g4x_disable_trickle_feed(struct drm_device *dev)
>  static void ironlake_init_clock_gating(struct drm_device *dev)
>  {
>         struct drm_i915_private *dev_priv = dev->dev_private;
> -       uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> -
> -       /*
> -        * Required for FBC
> -        * WaFbcDisableDpfcClockGating:snb
> -        */
> -       dspclk_gate |=
> -                  ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> -                  ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> +       uint32_t dspclk_gate =
> +               ILK_VRHUNIT_CLOCK_GATE_DISABLE |
> +               ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
>
>         I915_WRITE(PCH_3DCGDIS0,
>                    MARIUNIT_CLOCK_GATE_DISABLE |
> --
> 1.8.4.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni