[Intel-gfx] [PATCH] drm/i915: Avoid flicker with horizontal panning on 830GM

[Daniel Vetter]

On Sun, Sep 01, 2013 at 07:01:49PM +0200, Thomas Richter wrote:
> Dear intel-gfx developers,
> 
> When panning is enabled on the 830GM, horizontal panning creates a
> lot of flickering on specific pixel positions.
> After testing, I found that the reason for this is that panning
> works by altering the frame origin pointer, which,
> however, has certain alignment restrictions. If the pointer is not
> aligned correctly, the screen starts to flicker
> as, probably, DMA fails.
> 
> The following patch against drm/i915/intel_display.c fixes the issue
> by ensuring correct alignment. As result,
> horizontal panning works correctly, but is a bit "jumpy". Unclear
> whether the problem affects any other
> chipset revisions, thus the patch is currently only enabled for rev.2.

I've just looked at the docs and they only mention that the base address
must be pixel aligned. But it could very well be that the watermarks are a
bit off for your chipset. The below quick hack should test this theory.
-Daniel


diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dfdc7ad..990b1f4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1673,7 +1673,7 @@ static void i830_update_wm(struct drm_device *dev)
 				       dev_priv->display.get_fifo_size(dev, 0),
 				       4, latency_ns);
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
-	fwater_lo |= (3<<8) | planea_wm;
+	fwater_lo |= (3<<8) | 0;
 
 	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
 
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch