[Intel-gfx] [PATCH] drm/i915: Avoid flicker with horizontal panning on 830GM

[Daniel Vetter]

On Mon, Sep 02, 2013 at 03:58:59PM +0200, Thomas Richter wrote:
> Hi Daniel,
> 
> >I've just looked at the docs and they only mention that the base address
> >must be pixel aligned. But it could very well be that the watermarks are a
> >bit off for your chipset. The below quick hack should test this theory.
> >-Daniel
> >
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index dfdc7ad..990b1f4 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -1673,7 +1673,7 @@ static void i830_update_wm(struct drm_device *dev)
> >  				       dev_priv->display.get_fifo_size(dev, 0),
> >  				       4, latency_ns);
> >  	fwater_lo = I915_READ(FW_BLC)&  ~0xfff;
> >-	fwater_lo |= (3<<8) | planea_wm;
> >+	fwater_lo |= (3<<8) | 0;
> >
> >  	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
> >
> Checked with the above modifications. Unfortunately, the result is
> negative. With the above modifications and my changes commented out,
> the screen flickers in normal state (without panning) but in a
> different way: With the above enabled, you get a rather irregular
> almost pseudo-random flicker, and not the 60/30Hz flicker I see when
> panning horizontally. If I add horizontal panning, then I also get
> this irregular flicker, except when scrolling to the "forbidden
> positions" at which I get the regular hi-frequency flicker again.

Hm, I've probably botched the watermarks again. Can you please retest with
the below diff?

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dfdc7ad..b667ff0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1064,6 +1064,8 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 
 	DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 
+	wm_size = 0;
+
 	/* Don't promote wm_size to unsigned... */
 	if (wm_size > (long)wm->max_wm)
 		wm_size = wm->max_wm;

> However, now that I checked closer, I found that my patch has also a
> drawback, namely the hardware scroll position and the requested
> scroll position disagrees, i.e. the mouse pointer is not exactly
> where it should be, i.e. the mouse pointer hot-spot is off.
> 
> Is there a way to indicate the calling method what the actual
> panning/scroll position is if it is different from the requested
> position?
> 
> Is there a different method to scroll the screen than to adjust the
> screen origin? Old hardware had not only a screen pointer, but also
> a pixel-offset (horizontal scroll) register. Is there something like
> this on the 830M to work around the observed trouble?

The kms api doesn't really allow for such information to be passed around.
And since current userspace expects this to Just Work we need to be rather
careful with such hacks. Since the docs don't mention any such requirement
I think we should try a bit and figure out whether changing the watermarks
fixes this.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch