[Intel-gfx] [PATCH 08/11] drm/i915: Make i9xx_crtc_clock_get() work for PCH DPLLs

[Daniel Vetter]

On Fri, Sep 06, 2013 at 11:29:05PM +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Just add the 120MHz reference clock case, and magically the
> function appears to be ready to for PCH DPLLs.
> 
> Now, 120MHz might not always be correct, but we're already using
> hardocoded values for other platforms, so the situation isn't
> getting much worse.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 754de85..d89ea94 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7372,7 +7372,9 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
>  			return;
>  		}
>  
> -		if (IS_PINEVIEW(dev))
> +		if (HAS_PCH_SPLIT(dev))
> +			i9xx_clock(120000, &clock);

Check out ironlake_get_refclk for the more correct answer. You can check
for the ssc case by checking for the PLLB_REF_INPUT_SPREADSPECTRUMIN bit
in the dpll register.

One lofty idea I've had is that we'll track the dpll refclock in the pipe
config struct too. Then we can also double-check it when reconstructing
clocks. Finally I think the clock reconstruction dance should use the bits
in the dpll register and not magic knowledge ....

But that's a entire patch series of its own, probably part of the big
clock limits computation rework. So for this I'd just add a check for SSC
and snatch the SSC clock compuatation from ironlake_get_refclk.

Cheers, Daniel
> +		else if (IS_PINEVIEW(dev))
>  			pineview_clock(96000, &clock);
>  		else
>  			i9xx_clock(96000, &clock);
> -- 
> 1.8.1.5
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch