[Intel-gfx] [PATCH v2] drm/i915: Make i9xx_crtc_clock_get() work for PCH DPLLs

[Daniel Vetter]

On Fri, Sep 13, 2013 at 04:47:53PM +0300, Jani Nikula wrote:
> On Fri, 13 Sep 2013, Ville Syrjälä <ville.syrjala at linux.intel.com> wrote:
> > On Fri, Sep 13, 2013 at 04:04:03PM +0300, Jani Nikula wrote:
> >> On Mon, 09 Sep 2013, ville.syrjala at linux.intel.com wrote:
> >> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >> >
> >> > Add the 120MHz refernce clock case for PCH DPLLs.
> >> >
> >> > Also determine the reference clock frequency more accurately by
> >> > checking for the PLLB_REF_INPUT_SPREADSPECTRUMIN refclk input
> >> > mode. The gen2 code already checked it, but it stil assumed a
> >> > fixed 66MHz refclk. Instead we need to consult the VBT for the
> >> > real value.
> >> >
> >> > v2: Fix refclk for SSC panel case
> >> >
> >> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >> > ---
> >> >  drivers/gpu/drm/i915/intel_display.c | 32 +++++++++++++++++++++-----------
> >> >  1 file changed, 21 insertions(+), 11 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> > index 754de85..4f07292 100644
> >> > --- a/drivers/gpu/drm/i915/intel_display.c
> >> > +++ b/drivers/gpu/drm/i915/intel_display.c
> >> > @@ -7324,6 +7324,22 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
> >> >  	mutex_unlock(&crtc->mutex);
> >> >  }
> >> >  
> >> > +static int i9xx_pll_refclk(struct drm_device *dev,
> >> > +			   const struct intel_crtc_config *pipe_config)
> >> > +{
> >> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> >> > +	u32 dpll = pipe_config->dpll_hw_state.dpll;
> >> > +
> >> > +	if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
> >> 
> >> This seems wrong for at least gen3 and vlv. And it's a bit scary to go
> >> change gen2 but oh well...
> >
> > Why? i8xx_update_pll(), i9xx_update_pll() and ironlake_compute_dpll()
> > all have the same logic for setting that bit.
> 
> My Super Reliable(tm) gen3 spec says reserved for that value
> there. *shrug*.
> 
> > For VLV I agree. But the clock readout there is totally busted anyway,
> > so I don't care at this point.
> 
> Maybe Daniel can copy-paste something along those lines in the commit
> message. Or not. *shrug. :)

SSC refclocks is only used on lvds on those platforms, and lo and behold
lvds is restricted to pipe B on gen2/3. Magic!

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch