[Intel-gfx] [PATCH 1/4] drm/i915: WARN in case PIPECONF is already enabled

[Paulo Zanoni]

2013/9/20 Ville Syrjälä <ville.syrjala at linux.intel.com>:
> On Thu, Sep 19, 2013 at 05:07:26PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>>
>> After the modeset rework this really shouldn't be happening, so
>> transform it into a WARN. A stuck pipe is a bad signal and is one of
>> the things that can lead to full machine hangs.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 8fd13ab..5f1399d 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -1737,7 +1737,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
>>
>>       reg = PIPECONF(cpu_transcoder);
>>       val = I915_READ(reg);
>> -     if (val & PIPECONF_ENABLE)
>> +     if (WARN_ON(val & PIPECONF_ENABLE))
>>               return;
>
> You're forgetting QUIRK_PIPEA_FORCE.

Oh, I only did this to reinforce my point that 49% of the gen-agnostic
Display patches break some random Gen :)

Patches 2 and 3 depended on this patch, so for now let's ignore
patches 1-2-3 of the series (leaving only the Audio patch). I'll
resend this after we merge the current stuff.

Thanks for the review,
Paulo

>
>>
>>       I915_WRITE(reg, val | PIPECONF_ENABLE);
>> --
>> 1.8.3.1
>>
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>
> --
> Ville Syrjälä
> Intel OTC



-- 
Paulo Zanoni