[Intel-gfx] [PATCH] drm/i915: Fix VLV eDP timing v2

[Daniel Vetter]

On Wed, Sep 25, 2013 at 03:47:51PM +0800, Chon Ming Lee wrote:
> Fix the typo in previous commit for DP 1.62 divisor.
> drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
> 
> v2: sigh, the m1 div is 3.
> 
> Reported-by: Jesse Barnes <jbarnes at virtuousgeek.org> 
> Signed-off-by: Chon Ming Lee <chon.ming.lee at intel.com>

Ok, I'll try this one ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch