[Intel-gfx] [PATCH 5/7] drm/i915: Provide a bit more info when pipestat bits are wrong

Jesse Barnes jbarnes at virtuousgeek.org
Wed Apr 2 19:28:28 CEST 2014


On Mon, 31 Mar 2014 18:21:28 +0300
ville.syrjala at linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Print the enable_mask and status_mask from
> __i915_{enable,disable}_pipestat() when the called has messed them up
> somehow.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 6d26719..407742f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -503,8 +503,10 @@ __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>  
>  	assert_spin_locked(&dev_priv->irq_lock);
>  
> -	if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
> -	                 status_mask & ~PIPESTAT_INT_STATUS_MASK))
> +	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
> +		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
> +		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
> +		      pipe, enable_mask, status_mask))
>  		return;
>  
>  	if ((pipestat & enable_mask) == enable_mask)
> @@ -527,8 +529,10 @@ __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
>  
>  	assert_spin_locked(&dev_priv->irq_lock);
>  
> -	if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
> -	                 status_mask & ~PIPESTAT_INT_STATUS_MASK))
> +	if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
> +		      status_mask & ~PIPESTAT_INT_STATUS_MASK,
> +		      "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
> +		      pipe, enable_mask, status_mask))
>  		return;
>  
>  	if ((pipestat & enable_mask) == 0)

Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center



More information about the Intel-gfx mailing list