[Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

[Daniel Vetter]

On Thu, Apr 03, 2014 at 04:23:05PM +0100, Chris Wilson wrote:
> On Thu, Apr 03, 2014 at 05:16:16PM +0200, Daniel Vetter wrote:
> > btw the 1k thing at least on i865G is iirc just the writeout fifo between
> > the cpu and the gmch to paper over FSB latencies (or whatever irked hw
> > designers).
> 
> Isn't there a 1024 byte supercacheline for msaa as well? At least that
> sticks out in my mind from the discussions on when not to use eDRAM etc.

I've thought that was just a recommendation to not use eDRAM with
compressed msaa buffers since for those you only use the pixels on the
edges of primitives. And since one msaa pixel is less than the 1024bytes
the supercacheline is actual edram utilization for common workloads would
be horrible.

Or at least that's how I've interpreted the graphs and diagrams in the
docs. Afaik the coherency mocs bits for edram are still available on a 64
byte boundary, it's just the address tag which is much larger.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch