[Intel-gfx] [PATCH v4 5/6] drm/i915/vlv:Implement the WA 'WaDisable_RenderCache_OperationalFlush'

[Chris Wilson]

On Fri, Apr 04, 2014 at 06:35:21PM +0300, Ville Syrjälä wrote:
> On Fri, Apr 04, 2014 at 04:24:05PM +0100, Chris Wilson wrote:
> > On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gupta at intel.com wrote:
> > > From: Akash Goel <akash.goel at intel.com>
> > > 
> > > On Gen4+ platforms (except BDW), Render Cache Operational flush
> > > cannot be enabled.
> > > This WA is apparently required for all Gen4+ platforms,except BDW.
> > > In BDW, the bit has been repurposed otherwise.
> > > This has been tested only on vlv.
> > > 
> > > v2: Corrected the code regarding the wrong usage of
> > > MASKED_BIT_DISABLE (Chris)
> > > 
> > > v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville)
> > > 
> > > v4: Adding WA for g4x, crestline, broadwater (Ville)
> > > 
> > > Signed-off-by: Akash Goel <akash.goel at intel.com>
> > > Signed-off-by: Sourab Gupta <sourab.gupta at intel.com>
> > > Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > Note that we now have a redundant CM0_RC_OP_FLUSH_DISABLE (which fails
> > the name test anyway).
> 
> That's the correct name for the bit on gen3 AFAICS. Might be interesting
> to try to flip it on gen3 and see if we get moar fps :P

Hmm, that's true. Ok, keep the unused name ;-)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre