[Intel-gfx] [PATCH 6/6] drm/i915/vlv: re-order TX lane reset per latest spec

[Jesse Barnes]

This is supposed to fix some eDP PPS issues on some platforms.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_dp.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 98cf24f..34d01be 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1844,6 +1844,7 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = encoder->base.dev;
+	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 
@@ -1855,6 +1856,11 @@ static void vlv_enable_dp(struct intel_encoder *encoder)
 	if (!is_edp(intel_dp))
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 	intel_edp_panel_on(intel_dp);
+	mutex_lock(&dev_priv->dpio_lock);
+	vlv_dpio_write(dev_priv, intel_crtc->pipe, VLV_PCS_DW0(dport->port),
+			 DPIO_PCS_TX_LANE2_RESET |
+			 DPIO_PCS_TX_LANE1_RESET);
+	mutex_unlock(&dev_priv->dpio_lock);
 	vlv_wait_port_ready(dev_priv, dport);
 	edp_panel_vdd_off(intel_dp, true);
 	intel_dp_complete_link_train(intel_dp);
@@ -1918,9 +1924,6 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
 
 	/* Program Tx lane resets to default */
 	mutex_lock(&dev_priv->dpio_lock);
-	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
-			 DPIO_PCS_TX_LANE2_RESET |
-			 DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
 			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
-- 
1.8.4.2