[Intel-gfx] [PATCH 3/3] drm/i915/bdw: Use the GEN8 SRM when qeueing a flip

[Damien Lespiau]

On Tue, Apr 08, 2014 at 07:24:23AM +0100, Chris Wilson wrote:
> On Mon, Apr 07, 2014 at 11:20:14PM +0100, Damien Lespiau wrote:
> > On Mon, Apr 07, 2014 at 01:59:17PM -0700, Ben Widawsky wrote:
> > > Cool. This explains the bad DERRMR values I was seeing in in error
> > > states. I'm honestly didn't check if we actually need an SRM for BDW
> > > still, but I'll assume you did check.
> > 
> > Just checked, the LRI command still mentions that we need the SRM after
> > writes to the display engine.
> 
> It shouldn't explain the DERRMR values being incorrect though aiui. The
> SRM is to prevent system hangs from two concurrent writes, which never
> satisfied me as to how that prevents two different MMIO paths from
> accessing the same register cacheline simultaneously. Magic.

I've seen, elsewhere, this LRI not landing and DE_RRMR being the same
value as the reset value after the first flip post boot. Hence my IRC
question about the need to touch DE_RRMR if we're not waiting
explicitely for an event in the CS. This story may not end here!

-- 
Damien