[Intel-gfx] [PATCH 31/71] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating

[ville.syrjala at linux.intel.com]

From: Deepak S <deepak.s at intel.com>

v2: Added chv support for opcode to freq conversion and viceversa (Deepak)

Signed-off-by: Deepak S <deepak.s at intel.com>
[vsyrjala: Fix merge fubmle where the code ended up in
g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()]
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 392731a..2aa65ce 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5343,6 +5343,23 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 val;
+
+	mutex_lock(&dev_priv->rps.hw_lock);
+	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+
+	/* ToDo: Update the mem freq once the DDR rate is finalized [CHV] */
+	switch ((val >> 6) & 3) {
+	case 0:
+		dev_priv->mem_freq = 1600;
+		break;
+	case 1:
+		dev_priv->mem_freq = 2000;
+		break;
+	}
+
+	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
 
 	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 
@@ -6359,6 +6376,12 @@ int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
 	case 1333:
 		div = 16;
 		break;
+	case 1600:
+		div = 16;
+		break;
+	case 2000:
+		div = 16;
+		break;
 	default:
 		return -1;
 	}
@@ -6381,6 +6404,12 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
 	case 1333:
 		mul = 16;
 		break;
+	case 1600:
+		mul = 16;
+		break;
+	case 2000:
+		mul = 16;
+		break;
 	default:
 		return -1;
 	}
-- 
1.8.3.2