[Intel-gfx] [PATCH 33/71] drm/i915/chv: Fix for verifying PCBR address field.

[ville.syrjala at linux.intel.com]

From: Deepak S <deepak.s at intel.com>

This was fumbled in PCBR condition check during CHV RC6 Enable flag set

Issue introduced in

commit cb26b06c20094d69bcba191738960d053ac2c645
Author: Deepak S <deepak.s at intel.com>
Date:   Mon Dec 16 12:16:53 2013 +0530
Subject: drm/i915/chv: Enable Render Standby (RC6) for Cheeryview

v2: Commit message change (Jani)

v3: Mention the subject and author of the patch which introduced
the bug (Daniel)

v4: Use VLV_PCBR_ADDR_SHIFT instead of MASK (Jani)

v5: Commit message change. Add subject of the patch which introduced
the bug (Ville)

Signed-off-by: Deepak S <deepak.s at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e67b4a6..ac5047b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5294,6 +5294,7 @@ enum punit_power_well {
 #define GEN6_GT_GFX_RC6				0x138108
 #define GEN6_GT_GFX_RC6p			0x13810C
 #define GEN6_GT_GFX_RC6pp			0x138110
+#define VLV_PCBR_ADDR_SHIFT			12
 
 #define GEN6_PCODE_MAILBOX			0x138124
 #define   GEN6_PCODE_READY			(1<<31)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fb533a3..acaa1cf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3657,7 +3657,7 @@ static void cherryview_setup_pctx(struct drm_device *dev)
 	int pctx_size = 32*1024;
 
 	pcbr = I915_READ(VLV_PCBR);
-	if (pcbr >> 12 == 0) {
+	if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
 		/*
 		 * From the Gunit register HAS:
 		 * The Gfx driver is expected to program this register and ensure
@@ -3761,7 +3761,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
 	DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr);
 
 	/* 3: Enable RC6 */
-	if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE & (pcbr >> 12))
+	if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
+						(pcbr >> VLV_PCBR_ADDR_SHIFT))
 		rc6_mode = GEN6_RC_CTL_EI_MODE(1) | VLV_RC_CTL_CTX_RST_PARALLEL;
 
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
-- 
1.8.3.2