[Intel-gfx] [PATCH 11/15] drm/i915: vlv: disable RPM if RC6 is not enabled

[Imre Deak]

On Wed, 2014-04-09 at 11:36 -0300, Paulo Zanoni wrote:
> 2014-04-08 13:57 GMT-03:00 Imre Deak <imre.deak at intel.com>:
> > On VLV we depend on RC6 saving the GT render and media HW context before
> > going to D3 state, so disable RPM if RC6 is not enabled.
> 
> Maybe this problem affects other platforms too, and we just didn't
> notice because RC6 is always enabled on them. Did we test this on the
> other platforms?

No, tbh I wanted to submit this as early as possible. I think now with
patch 10/15 RPM should be disabled for all GEN6+ platforms. 

> Do we have a way to disable RC6 at runtime? If yes, then we could
> probably try to write some test at pm_pc8.c.

It's a module option, but I can look into adding a test for it.

--Imre

> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_drv.h |  2 ++
> >  drivers/gpu/drm/i915/intel_pm.c  | 29 ++++++++++++++++++++++++++++-
> >  2 files changed, 30 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index 7f4e873..b4fcd14 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -902,6 +902,7 @@ void intel_cleanup_gt_powersave(struct drm_device *dev);
> >  void intel_enable_gt_powersave(struct drm_device *dev);
> >  void intel_disable_gt_powersave(struct drm_device *dev);
> >  void intel_reset_gt_powersave(struct drm_device *dev);
> > +bool valleyview_rc6_enabled(struct drm_device *dev);
> >  void ironlake_teardown_rc6(struct drm_device *dev);
> >  void gen6_update_ring_freq(struct drm_device *dev);
> >  void gen6_rps_idle(struct drm_i915_private *dev_priv);
> > @@ -909,6 +910,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv);
> >  void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
> >  void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
> >  void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
> > +void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
> >  void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
> >  void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
> >  void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index c082936..15e6b38 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3660,6 +3660,11 @@ static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
> >         valleyview_cleanup_pctx(dev);
> >  }
> >
> > +bool valleyview_rc6_enabled(struct drm_device *dev)
> > +{
> > +       return intel_enable_rc6(dev) & INTEL_RC6_ENABLE;
> > +}
> > +
> >  static void valleyview_enable_rps(struct drm_device *dev)
> >  {
> >         struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -3709,7 +3714,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
> >                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> >                                       VLV_MEDIA_RC6_COUNT_EN |
> >                                       VLV_RENDER_RC6_COUNT_EN));
> > -       if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
> > +       if (valleyview_rc6_enabled(dev))
> >                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
> >
> >         intel_print_rc6_info(dev, rc6_mode);
> > @@ -6010,6 +6015,18 @@ void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
> >         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
> >  }
> >
> > +void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
> > +{
> > +       struct drm_device *dev = dev_priv->dev;
> > +       struct device *device = &dev->pdev->dev;
> > +
> > +       if (!HAS_RUNTIME_PM(dev))
> > +               return;
> > +
> > +       WARN(dev_priv->pm.suspended, "Can't get nosync-ref while suspended.\n");
> > +       pm_runtime_get_noresume(device);
> > +}
> > +
> >  void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
> >  {
> >         struct drm_device *dev = dev_priv->dev;
> > @@ -6032,6 +6049,13 @@ void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
> >
> >         pm_runtime_set_active(device);
> >
> > +       /*
> > +        * On Valleyview we depend on the HW RC6 power context save/restore
> > +        * mechanism for RPM, so leave RPM disabled if RC6 is disabled.
> > +        */
> > +       if (IS_VALLEYVIEW(dev) && !valleyview_rc6_enabled(dev))
> > +               return;
> > +
> >         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
> >         pm_runtime_mark_last_busy(device);
> >         pm_runtime_use_autosuspend(device);
> > @@ -6047,6 +6071,9 @@ void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
> >         if (!HAS_RUNTIME_PM(dev))
> >                 return;
> >
> > +       if (IS_VALLEYVIEW(dev) && !valleyview_rc6_enabled(dev))
> > +               return;
> > +
> >         /* Make sure we're not suspended first. */
> >         pm_runtime_get_sync(device);
> >         pm_runtime_disable(device);
> > --
> > 1.8.4
> >
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> 
> 
>