[Intel-gfx] [PATCH 71/71] drm/i915/chv: Handle video DIP registers on CHV

[Damien Lespiau]

On Wed, Apr 09, 2014 at 01:29:09PM +0300, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> The DIP registers are a mess on VLV and CHV. The register block on pipe
> A is different than the register block on pipes B and C. In order to
> handle that using the pipe offsets, we'd need a new pipe offset per
> register, which seems wasteful. So instead just use the _PIPE3() macro
> to handle these registers.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++++++-----
>  1 file changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9fed8ca..14e8de3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4784,8 +4784,7 @@ enum punit_power_well {
>  #define _PCH_TRANSA_LINK_M2	0xe0048
>  #define _PCH_TRANSA_LINK_N2	0xe004c
>  
> -/* Per-transcoder DIP controls */
> -
> +/* Per-transcoder DIP controls (PCH) */
>  #define _VIDEO_DIP_CTL_A         0xe0200
>  #define _VIDEO_DIP_DATA_A        0xe0208
>  #define _VIDEO_DIP_GCP_A         0xe0210
> @@ -4798,6 +4797,7 @@ enum punit_power_well {
>  #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
>  #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
>  
> +/* Per-transcoder DIP controls (VLV) */
>  #define VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
>  #define VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
>  #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
> @@ -4806,12 +4806,19 @@ enum punit_power_well {
>  #define VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
>  #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
>  
> +#define CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
> +#define CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
> +#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
> +
>  #define VLV_TVIDEO_DIP_CTL(pipe) \
> -	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
> +	_PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
> +	       VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
>  #define VLV_TVIDEO_DIP_DATA(pipe) \
> -	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
> +	_PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
> +	       VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
>  #define VLV_TVIDEO_DIP_GCP(pipe) \
> -	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
> +	_PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
> +		VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
>  
>  /* Haswell DIP controls */
>  #define HSW_VIDEO_DIP_CTL_A		0x60200
> -- 
> 1.8.3.2
> 
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