[Intel-gfx] [PATCH 30/71] drm/i915/chv: Enable PM interrupts when we in CHV turbo initialize sequence.

[Deepak S]

On Wednesday 09 April 2014 06:36 PM, Chris Wilson wrote:
> On Wed, Apr 09, 2014 at 01:28:28PM +0300, ville.syrjala at linux.intel.com wrote:
>> +static void gen8_enable_rps_interrupts(struct drm_device *dev)
>> +{
>> +	struct drm_i915_private *dev_priv = dev->dev_private;
>> +
>> +	/* Clear out any stale interrupts first */
>> +	spin_lock_irq(&dev_priv->irq_lock);
>> +	WARN_ON(dev_priv->rps.pm_iir);
>> +	I915_WRITE(GEN8_GT_IIR(2), I915_READ(GEN8_GT_IIR(2)));
>> +	dev_priv->pm_irq_mask &= ~GEN6_PM_RPS_EVENTS;
>> +	I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
>> +	spin_unlock_irq(&dev_priv->irq_lock);
>> +
>> +	I915_WRITE(GEN8_GT_IER(2), GEN6_PM_RPS_EVENTS);
>> +	/* only unmask PM interrupts we need. Mask all others. */
>> +	I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
> PMINTRMSK handling is now a part of set_rps (and so this line is
> redundant).
> -Chris

Thanks Chris. I will make the changes based on the current nightly code