[Intel-gfx] [PATCH 49/71] drm/i915/chv: Add CHV display support

[Jani Nikula]

On Wed, 09 Apr 2014, ville.syrjala at linux.intel.com wrote:
> From: Rafael Barbalho <rafael.barbalho at intel.com>
>
> Add support for the third pipe in cherrview
>
> Signed-off-by: Rafael Barbalho <rafael.barbalho at intel.com>
> [vsyrjala: slightly massaged the patch]
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |  7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++---
>  2 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2415fa2..c5e9fa8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,12 @@ static struct drm_driver driver;
>  	.dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
>  	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
>  
> +#define GEN_CHV_PIPEOFFSETS \
> +       .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, CHV_PIPE_C_OFFSET }, \
> +       .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, CHV_TRANSCODER_C_OFFSET, }, \
> +       .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, CHV_DPLL_C_OFFSET }, \
> +       .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, CHV_DPLL_C_MD_OFFSET }, \
> +       .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, CHV_PALETTE_C_OFFSET }
>  
>  static const struct intel_device_info intel_i830_info = {
>  	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> @@ -286,6 +292,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>  	.is_valleyview = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
> +	GEN_CHV_PIPEOFFSETS,

These use spaces for indentation. Please fix.

BR,
Jani.


>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7587752..3831d84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1430,6 +1430,7 @@ enum punit_power_well {
>   */
>  #define DPLL_A_OFFSET 0x6014
>  #define DPLL_B_OFFSET 0x6018
> +#define CHV_DPLL_C_OFFSET 0x6030
>  #define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
>  		    dev_priv->info.display_mmio_offset)
>  
> @@ -1521,6 +1522,7 @@ enum punit_power_well {
>  
>  #define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
>  #define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
> +#define CHV_DPLL_C_MD_OFFSET 0x603c
>  #define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
>  		       dev_priv->info.display_mmio_offset)
>  
> @@ -1717,6 +1719,7 @@ enum punit_power_well {
>   */
>  #define PALETTE_A_OFFSET 0xa000
>  #define PALETTE_B_OFFSET 0xa800
> +#define CHV_PALETTE_C_OFFSET 0xc000
>  #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
>  		       dev_priv->info.display_mmio_offset)
>  
> @@ -2206,6 +2209,7 @@ enum punit_power_well {
>  #define TRANSCODER_A_OFFSET 0x60000
>  #define TRANSCODER_B_OFFSET 0x61000
>  #define TRANSCODER_C_OFFSET 0x62000
> +#define CHV_TRANSCODER_C_OFFSET 0x63000
>  #define TRANSCODER_EDP_OFFSET 0x6f000
>  
>  #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
> @@ -3533,9 +3537,10 @@ enum punit_power_well {
>  #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
>  #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
>  
> -#define PIPE_A_OFFSET	0x70000
> -#define PIPE_B_OFFSET	0x71000
> -#define PIPE_C_OFFSET	0x72000
> +#define PIPE_A_OFFSET		0x70000
> +#define PIPE_B_OFFSET		0x71000
> +#define PIPE_C_OFFSET		0x72000
> +#define CHV_PIPE_C_OFFSET	0x74000
>  /*
>   * There's actually no pipe EDP. Some pipe registers have
>   * simply shifted from the pipe to the transcoder, while
> -- 
> 1.8.3.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center