[Intel-gfx] [PATCH] drm/i915/bdw: BDW swizzling in done by the memory controller

[Daniel Vetter]

On Fri, Apr 11, 2014 at 1:10 PM, Damien Lespiau
<damien.lespiau at intel.com> wrote:
> On Fri, Apr 11, 2014 at 11:09:03AM +0200, Daniel Vetter wrote:
>> So not yet sold on the story here, at least for gen8/bdw. Apparently
>> people haven't screamed about this yet, so it probably works.
>
> Having thought about it a bit more, I don't see how the CPU side would
> know about the tiling layout of the surfaces it accesses, so the
> remaining options I see:
>
>   - we still need to swizzle the address on the CPU side
>   - bit 6 swizzling for X/Y tiling is just gone and the optimal use of
>     the RAM is left to the memory controller. If that's the case, we
>     should see things failing soon enough
>
> So, until any failure case, meh. Just one thing to remember is that the
> swizzling bits we set are possibly reserved and may be no-ops.

That's very easy to figure out. Set the bit in TILE_CTL and
GAMT_ARBMODE differently and see what happens. blt vs gtt mmap access
would be different. igt has testcases which will catch this.

At least on simulation this blew up rather badly ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch