[Intel-gfx] [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv

[Gupta, Sourab]

On Tue, 2014-04-01 at 10:53 +0530, sourab gupta wrote:
> On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote:
> > On Mon, 2014-03-24 at 17:56 +0000, Lespiau, Damien wrote:
> > > On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gupta at intel.com wrote:
> > > > From: Akash Goel <akash.goel at intel.com>
> > > > 
> > > > For disabling L3 clock gating we need to set bit 25 of MMIO
> > > > register 940c. Earlier this was being done by just writing 1
> > > > into bit 25 and resetting all other bits.
> > > > This patch modifies the routine to read-modify-write of the
> > > > register, so that the values of other bits are not destroyed.
> > > > 
> > > > v2: Modifying the comments and the patch commit message (Chris)
> > > 
> > > This patch commit message lacks the most important information: which
> > > bit are we setting back to 0 and we shouldn't, and why is that
> > > important? We do direct writes to other registers in that function (for
> > > instance (MI_ARB_VLV just below).
> > > 
> > Hi Damien,
> > The reset value of the register is 0x00F80003. Therefore, if we directly
> > set only bit 25 to 1, without caring about other bits, the following reg
> > bits will be affected (bits 1:0, bits 23:19).
> > This doesn't seem to be the case with other regs where we are writing
> > directly (MI_ARB_VLV ) whose default value is 0.
> > So, by this commit we're just trying to set only the bit which we really
> > want to change.
> > 
> > Regards,
> > Sourab
> > 
> > 
> Hi Damien,
> Please provide your comments on the above explanation. I'll add more
> information to the commit message regarding the same, if it is okay.
> 
> Thanks,
> Sourab
> 
Hi Damien,

Waiting for feedback on the patch and the explanation. Can you please
let us know if the explained reason is good enough for the patch to be
considered. If so, it can be added to the commit message.

Regards,
Sourab