[Intel-gfx] [RFC] xf86-video-intel: enable hw-generated binding tables

[Abdiel Janulgue]

This patch series enables resource streamer for xf86-video-intel UXA.

Fixes i965 Mesa driver that makes use of resource streamer optimization
to survive a full piglit run without bricking the machine. Previously,
I get random hungs when doing a full piglit round when enabling RS. 
After months of head-scratching, I noticed I didn't quite pay attention
to this small detail in bspec:

 "The binding table generator feature has a simple all or nothing
  model. If HW generated binding tables are enabled, the driver must enable
  the pool and use 3D_HW_BINDING_TABLE_POINTER_* commands."

I realized that our xf86-video-intel driver is piping out 3D commands
as well that used the older manual-generated binding table format
that caused a conflict when Mesa is using the hw-generated binding table 
format.

I didn't touch the SNA and video acceleration paths yet. Please let me know
if I'm on the right track.

To use the feature, set in xorg.conf:

Option "ResourceStreamer" "true"

 src/intel_options.c         |    1 +
 src/intel_options.h         |    1 +
 src/uxa/i965_3d.c           |    5 ++-
 src/uxa/i965_reg.h          |    8 +++++
 src/uxa/i965_render.c       |   78 +++++++++++++++++++++++++++++++++++--------
 src/uxa/intel.h             |    3 ++
 src/uxa/intel_batchbuffer.c |    7 ++--
 src/uxa/intel_driver.c      |   10 +++++-
 8 files changed, 94 insertions(+), 19 deletions(-)

Abdiel Janulgue (2):

[PATCH 1/2] xf86-video-intel: Add "ResourceStreamer" option
[PATCH 2/2] xf86-video-intel: Enable hw-generated binding tables for