[Intel-gfx] [bisect result] Re: 3.15-rc2: i915 regression: only top 20% of screen works in X

[Chris Wilson]

On Thu, Apr 24, 2014 at 09:40:38PM +0200, Pavel Machek wrote:
> Hi!
> 
> > And if you can indeed reliably reproduce this a bisect could be really useful.
> 
> And we have a winner here :-)
> 
> Ok, it was not as painfull as I feared.
> 
> It does not revert cleanly, but doing it by hand was not that bad.

Oh my. That is bizarre, can you check whether you have

commit 9991ae787a0c87fe7c783b4b6f4754c3cdbb6213
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Wed Apr 2 16:36:07 2014 +0100

    drm/i915: Move all ring resets before setting the HWS page

in your latest kernel? That just makes

> commit a51435a3137ad8ae75c288c39bd2d8b2696bae8f
> Author: Naresh Kumar Kachhi <naresh.kumar.kachhi at intel.com>
> Date:   Wed Mar 12 16:39:40 2014 +0530
> 
>     drm/i915: disable rings before HW status page setup

more consistent wrt g4x.

To confirm, on drm-intel-nightly you used a patch like:

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 36a62af..ce6186a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -494,6 +494,11 @@ static int init_ring_common(struct intel_ring_buffer *ring)
               I915_READ_TAIL(ring),
               I915_READ_START(ring));
 
+       if (I915_NEED_GFX_HWS(dev))
+               intel_ring_setup_status_page(ring);
+       else
+               ring_setup_phys_status_page(ring);
+
        if (!stop_ring(ring)) {
                /* G45 ring initialization often fails to reset head to zero */
                DRM_DEBUG_KMS("%s head not reset to zero "
@@ -517,11 +522,6 @@ static int init_ring_common(struct intel_ring_buffer *ring)
                }
        }
 
-       if (I915_NEED_GFX_HWS(dev))
-               intel_ring_setup_status_page(ring);
-       else
-               ring_setup_phys_status_page(ring);
-
 reset:
        /* Initialize the ring. This must happen _after_ we've cleared the ring
         * registers with the above sequence (the readback of the HEAD registers


-- 
Chris Wilson, Intel Open Source Technology Centre