[Intel-gfx] [PATCH 31/66] drm/i915: Move lowfreq_avail around a bit in ilk/hsw_crtc_mode_set

[Daniel Vetter]

Now this really should be in the pipe config somewhere, but till now
it isn't. We can at least move it up a bit next to all the other pll
code since intel_dp_set_m_n really doesn't depend upon this.

This is just prep work so that moving all the hw frobbing code from
->crtc_mode_set to ->crtc_enable is clean.

v2: Do the same for haswell while at it, not just for ivb.

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5740e08c3d2e..d6878d07a516 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6620,14 +6620,14 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 	} else
 		intel_put_shared_dpll(intel_crtc);
 
-	if (intel_crtc->config.has_dp_encoder)
-		intel_dp_set_m_n(intel_crtc);
-
 	if (is_lvds && has_reduced_clock && i915.powersave)
 		intel_crtc->lowfreq_avail = true;
 	else
 		intel_crtc->lowfreq_avail = false;
 
+	if (intel_crtc->config.has_dp_encoder)
+		intel_dp_set_m_n(intel_crtc);
+
 	intel_set_pipe_timings(intel_crtc);
 
 	if (intel_crtc->config.has_pch_encoder) {
@@ -7124,11 +7124,11 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
 		return -EINVAL;
 	intel_ddi_pll_enable(intel_crtc);
 
+	intel_crtc->lowfreq_avail = false;
+
 	if (intel_crtc->config.has_dp_encoder)
 		intel_dp_set_m_n(intel_crtc);
 
-	intel_crtc->lowfreq_avail = false;
-
 	intel_set_pipe_timings(intel_crtc);
 
 	if (intel_crtc->config.has_pch_encoder) {
-- 
1.8.1.4