[Intel-gfx] [PATCH 42/71] drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV

[Paulo Zanoni]

2014-04-09 7:28 GMT-03:00  <ville.syrjala at linux.intel.com>:
> From: Rafael Barbalho <rafael.barbalho at intel.com>
>
> Cherryview also needs this WA.

At least on the chv_rebase tree, this WA is implemented for BDW but it
is not documented as pre-prod only, and its name is not there. We
should probably add a comment documenting the name and the fact that
it is also pre-prod on BDW.


>
> Signed-off-by: Rafael Barbalho <rafael.barbalho at intel.com>
> [vsyrjala: Looks like it's for pre-prodution hw only]
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 468fe37..60f876c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5405,6 +5405,10 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>         /* WaDisableSDEUnitClockGating:chv */
>         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
> +       /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
> +       I915_WRITE(HALF_SLICE_CHICKEN3,
> +                  _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));

I could not find information anywhere if this is the correct
implementation. Can you please provide me pointers to the doc you
used? The links on Collab seem broken.

Thanks,
Paulo

>  }
>
>  static void g4x_init_clock_gating(struct drm_device *dev)
> --
> 1.8.3.2
>
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-- 
Paulo Zanoni