[Intel-gfx] [PATCH v3] drm/i915: Add boot paramter to control rps boost at boot time.
Chris Wilson
chris at chris-wilson.co.uk
Mon Apr 28 16:55:56 CEST 2014
On Mon, Apr 28, 2014 at 08:17:04PM +0530, deepak.s at linux.intel.com wrote:
> From: Deepak S <deepak.s at linux.intel.com>
>
> We are adding a module paramter to control rps boost. By default, we
> enable the boost for better performace. Based on the need (perf/power)
> we can either enable/disable.
>
> v2: Addressed rps default comment (Jani)
>
> v3: Use bool to represent the boot parameter (Ville).
>
> Signed-off-by: Deepak S <deepak.s at linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/i915_params.c | 5 +++++
> 3 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e81feab..6136aab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1945,6 +1945,7 @@ struct i915_params {
> bool reset;
> bool disable_display;
> bool disable_vtd_wa;
> + bool enable_rps_boost;
> };
> extern struct i915_params i915 __read_mostly;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index b00a77e..f2b3262 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1049,7 +1049,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
>
> timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
>
> - if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
> + if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv) && i915.enable_rps_boost) {
The separate INTEL_INFO was because this used to be a neat
dev_priv->info.gen dereference (and dev used to not be derivable from
file_priv, which itself may be NULL here), but please don't add another
predicate that means can_wait_boost().
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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