[Intel-gfx] [PATCH] drm/i915: Rename defines for selection of ddi buffer translation slot

[sonika.jindal at intel.com]

From: Sonika Jindal <sonika.jindal at intel.com>

Renaming the HSW-specific macros for ddi buffer translation slot to denote the
slot and not the vswing/pre-emph values as they are platform-dependent.

This patch is based on top of the patch series for renaming the DP training
vswing/pre-emph defines:
http://lists.freedesktop.org/archives/intel-gfx/2014-August/050123.html

Signed-off-by: Sonika Jindal <sonika.jindal at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |   18 +++++++++---------
 drivers/gpu/drm/i915/intel_ddi.c |   20 ++++++++++----------
 drivers/gpu/drm/i915/intel_dp.c  |   20 ++++++++++----------
 3 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc13961..81c6b51 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5888,15 +5888,15 @@ enum punit_power_well {
 #define DDI_BUF_CTL_B				0x64100
 #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
 #define  DDI_BUF_CTL_ENABLE			(1<<31)
-#define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
-#define  DDI_BUF_EMP_400MV_3_5DB_HSW		(1<<24)   /* Sel1 */
-#define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
-#define  DDI_BUF_EMP_400MV_9_5DB_HSW		(3<<24)   /* Sel3 */
-#define  DDI_BUF_EMP_600MV_0DB_HSW		(4<<24)   /* Sel4 */
-#define  DDI_BUF_EMP_600MV_3_5DB_HSW		(5<<24)   /* Sel5 */
-#define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
-#define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
-#define  DDI_BUF_EMP_800MV_3_5DB_HSW		(8<<24)   /* Sel8 */
+#define  DDI_BUF_TRANS_SELECT_0		(0<<24)
+#define  DDI_BUF_TRANS_SELECT_1		(1<<24)
+#define  DDI_BUF_TRANS_SELECT_2		(2<<24)
+#define  DDI_BUF_TRANS_SELECT_3		(3<<24)
+#define  DDI_BUF_TRANS_SELECT_4		(4<<24)
+#define  DDI_BUF_TRANS_SELECT_5		(5<<24)
+#define  DDI_BUF_TRANS_SELECT_6		(6<<24)
+#define  DDI_BUF_TRANS_SELECT_7		(7<<24)
+#define  DDI_BUF_TRANS_SELECT_8		(8<<24)
 #define  DDI_BUF_EMP_MASK			(0xf<<24)
 #define  DDI_BUF_PORT_REVERSAL			(1<<16)
 #define  DDI_BUF_IS_IDLE			(1<<7)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ca1f9a8..a616747 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -242,15 +242,15 @@ void intel_prepare_ddi(struct drm_device *dev)
 }
 
 static const long hsw_ddi_buf_ctl_values[] = {
-	DDI_BUF_EMP_400MV_0DB_HSW,
-	DDI_BUF_EMP_400MV_3_5DB_HSW,
-	DDI_BUF_EMP_400MV_6DB_HSW,
-	DDI_BUF_EMP_400MV_9_5DB_HSW,
-	DDI_BUF_EMP_600MV_0DB_HSW,
-	DDI_BUF_EMP_600MV_3_5DB_HSW,
-	DDI_BUF_EMP_600MV_6DB_HSW,
-	DDI_BUF_EMP_800MV_0DB_HSW,
-	DDI_BUF_EMP_800MV_3_5DB_HSW
+	DDI_BUF_TRANS_SELECT_0,
+	DDI_BUF_TRANS_SELECT_1,
+	DDI_BUF_TRANS_SELECT_2,
+	DDI_BUF_TRANS_SELECT_3,
+	DDI_BUF_TRANS_SELECT_4,
+	DDI_BUF_TRANS_SELECT_5,
+	DDI_BUF_TRANS_SELECT_6,
+	DDI_BUF_TRANS_SELECT_7,
+	DDI_BUF_TRANS_SELECT_8
 };
 
 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
@@ -402,7 +402,7 @@ void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 		enc_to_dig_port(&encoder->base);
 
 	intel_dp->DP = intel_dig_port->saved_port_bits |
-		DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
+		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT_0;
 	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 
 }
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c2b3075..7a8ee50 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2854,29 +2854,29 @@ intel_hsw_signal_levels(uint8_t train_set)
 					 DP_TRAIN_PRE_EMPHASIS_MASK);
 	switch (signal_levels) {
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPHASIS_LEVEL_0:
-		return DDI_BUF_EMP_400MV_0DB_HSW;
+		return DDI_BUF_TRANS_SELECT_0;
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPHASIS_LEVEL_1:
-		return DDI_BUF_EMP_400MV_3_5DB_HSW;
+		return DDI_BUF_TRANS_SELECT_1;
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPHASIS_LEVEL_2:
-		return DDI_BUF_EMP_400MV_6DB_HSW;
+		return DDI_BUF_TRANS_SELECT_2;
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPHASIS_LEVEL_3:
-		return DDI_BUF_EMP_400MV_9_5DB_HSW;
+		return DDI_BUF_TRANS_SELECT_3;
 
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPHASIS_LEVEL_0:
-		return DDI_BUF_EMP_600MV_0DB_HSW;
+		return DDI_BUF_TRANS_SELECT_4;
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPHASIS_LEVEL_1:
-		return DDI_BUF_EMP_600MV_3_5DB_HSW;
+		return DDI_BUF_TRANS_SELECT_5;
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPHASIS_LEVEL_2:
-		return DDI_BUF_EMP_600MV_6DB_HSW;
+		return DDI_BUF_TRANS_SELECT_6;
 
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPHASIS_LEVEL_0:
-		return DDI_BUF_EMP_800MV_0DB_HSW;
+		return DDI_BUF_TRANS_SELECT_7;
 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPHASIS_LEVEL_1:
-		return DDI_BUF_EMP_800MV_3_5DB_HSW;
+		return DDI_BUF_TRANS_SELECT_8;
 	default:
 		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
 			      "0x%x\n", signal_levels);
-		return DDI_BUF_EMP_400MV_0DB_HSW;
+		return DDI_BUF_TRANS_SELECT_0;
 	}
 }
 
-- 
1.7.10.4