[Intel-gfx] [PATCH 2/2] drm/i915: Initialize the aliasing ppgtt as part of global gtt

[Thierry, Michel]

> -----Original Message-----
> From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch]
> Sent: Wednesday, August 06, 2014 7:20 PM
> To: Intel Graphics Development
> Cc: Daniel Vetter; Thierry, Michel; Ville Syrjälä
> Subject: [PATCH 2/2] drm/i915: Initialize the aliasing ppgtt as part of global gtt
> 
> Stuffing this into the context setup code doesn't make a lot of sense.
> Also reusing the real ppgtt setup code makes even less sense since the
> aliasing ppgtt isn't a real address space. Leaving all that stuff
> unitialized will make sure that we catch any abusers promptly.
> 
> This is also a prep work to clean up the context->ppgtt link.
> 
> v2: Fix up the logic fail, I've fumbled it so badly to completely
> disable ppgtt on gen6. Spotted by Ville and Michel. Also move around
> the pde write into the gen6 init function, since otherwise it won't
> work at all.
> 
> v3: Only initialize the aliasing ppgtt when we actually enable it.
> 
> Cc: "Thierry, Michel" <michel.thierry at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 13 +---------
>  drivers/gpu/drm/i915/i915_gem_gtt.c     | 42 +++++++++++++++++++++++-
> ---------
>  2 files changed, 31 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index 4af5f05b24e8..07f4d060575b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -276,17 +276,6 @@ i915_gem_create_context(struct drm_device *dev,
>  			goto err_unpin;
>  		} else
>  			ctx->vm = &ppgtt->base;
> -
> -		/* This case is reserved for the global default context and
> -		 * should only happen once. */
> -		if (is_global_default_ctx) {
> -			if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) {
> -				ret = -EEXIST;
> -				goto err_unpin;
> -			}
> -
> -			dev_priv->mm.aliasing_ppgtt = ppgtt;
> -		}
>  	} else if (USES_PPGTT(dev)) {
>  		/* For platforms which only have aliasing PPGTT, we fake the
>  		 * address space and refcounting. */
> @@ -361,7 +350,7 @@ int i915_gem_context_init(struct drm_device *dev)
>  		}
>  	}
> 
> -	ctx = i915_gem_create_context(dev, NULL, USES_PPGTT(dev));
> +	ctx = i915_gem_create_context(dev, NULL,
> USES_FULL_PPGTT(dev));
>  	if (IS_ERR(ctx)) {
>  		DRM_ERROR("Failed to create default global context (error
> %ld)\n",
>  			  PTR_ERR(ctx));
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index bf70ab44b968..653a1166a3fa 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1141,35 +1141,38 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt
> *ppgtt)
>  			 ppgtt->node.size >> 20,
>  			 ppgtt->node.start / PAGE_SIZE);
> 
> +	gen6_write_pdes(ppgtt);
> +	DRM_DEBUG("Adding PPGTT at offset %x\n",
> +		  ppgtt->pd_offset << 10);
> +
>  	return 0;
>  }
> 
> -int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
> +int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int ret = 0;
> 
>  	ppgtt->base.dev = dev;
>  	ppgtt->base.scratch = dev_priv->gtt.base.scratch;
> 
>  	if (INTEL_INFO(dev)->gen < 8)
> -		ret = gen6_ppgtt_init(ppgtt);
> +		return gen6_ppgtt_init(ppgtt);
>  	else if (IS_GEN8(dev))
> -		ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
> +		return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
>  	else
>  		BUG();
> +}
> +int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int ret = 0;
> 
> -	if (!ret) {
> -		struct drm_i915_private *dev_priv = dev->dev_private;
> +	ret = __hw_ppgtt_init(dev, ppgtt);
> +	if (ret == 0) {
>  		kref_init(&ppgtt->ref);
>  		drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
>  			    ppgtt->base.total);
>  		i915_init_vm(dev_priv, &ppgtt->base);
> -		if (INTEL_INFO(dev)->gen < 8) {
> -			gen6_write_pdes(ppgtt);
> -			DRM_DEBUG("Adding PPGTT at offset %x\n",
> -				  ppgtt->pd_offset << 10);
> -		}
>  	}
> 
>  	return ret;
> @@ -1710,6 +1713,7 @@ int i915_gem_setup_global_gtt(struct drm_device
> *dev,
>  	struct drm_mm_node *entry;
>  	struct drm_i915_gem_object *obj;
>  	unsigned long hole_start, hole_end;
> +	int ret;
> 
>  	BUG_ON(mappable_end > end);
> 
> @@ -1721,7 +1725,7 @@ int i915_gem_setup_global_gtt(struct drm_device
> *dev,
>  	/* Mark any preallocated objects as occupied */
>  	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
>  		struct i915_vma *vma = i915_gem_obj_to_vma(obj,
> ggtt_vm);
> -		int ret;
> +
>  		DRM_DEBUG_KMS("reserving preallocated space: %lx +
> %zx\n",
>  			      i915_gem_obj_ggtt_offset(obj), obj->base.size);
> 
> @@ -1748,6 +1752,20 @@ int i915_gem_setup_global_gtt(struct drm_device
> *dev,
>  	/* And finally clear the reserved guard page */
>  	ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
> 
> +	if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
> +		struct i915_hw_ppgtt *ppgtt;
> +
> +		ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
> +		if (!ppgtt)
> +			return -ENOMEM;
> +
> +		ret = __hw_ppgtt_init(dev, ppgtt);
> +		if (ret != 0)
> +			return ret;
> +
> +		dev_priv->mm.aliasing_ppgtt = ppgtt;
> +	}
> +
>  	return 0;
>  }
> 
Reviewed-by: Michel Thierry <michel.thierry at intel.com>
> --
> 1.9.3

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