[Intel-gfx] [PATCH v2] drm/i915: Don't warn if we restore pm interrupts during reset
Daniel Vetter
daniel at ffwll.ch
Thu Aug 14 16:23:16 CEST 2014
On Thu, Aug 14, 2014 at 03:46:43PM +0300, Mika Kuoppala wrote:
> We lost the software state tracking due to reset, so don't
> complain if it doesn't match.
This sounds more like gpu reset should be a bit more careful (even more
careful than we already are compared to earlier kernels) with making sure
the irq state is still sane after a reset?
Or what exactly is the failure mode here? The commit message lacks a bit
details in form of a nice text or even better: A testcase ;-)
Thanks, Daniel
>
> v2: fix build error
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 12f4e14..7a1309c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3593,7 +3593,8 @@ static void gen8_enable_rps_interrupts(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> spin_lock_irq(&dev_priv->irq_lock);
> - WARN_ON(dev_priv->rps.pm_iir);
> + if (!i915_reset_in_progress(&dev_priv->gpu_error))
> + WARN_ON(dev_priv->rps.pm_iir);
> gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
> I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
> spin_unlock_irq(&dev_priv->irq_lock);
> @@ -3604,7 +3605,8 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> spin_lock_irq(&dev_priv->irq_lock);
> - WARN_ON(dev_priv->rps.pm_iir);
> + if (!i915_reset_in_progress(&dev_priv->gpu_error))
> + WARN_ON(dev_priv->rps.pm_iir);
> gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
> I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
> spin_unlock_irq(&dev_priv->irq_lock);
> --
> 1.7.9.5
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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