[Intel-gfx] [PATCH 2/2] igt/gem_workarounds: igt to test workaround registers
Daniel Vetter
daniel at ffwll.ch
Tue Aug 26 14:57:40 CEST 2014
On Wed, Aug 20, 2014 at 03:52:12PM +0100, Arun Siluvery wrote:
> Some of the workarounds are lost followed by a gpu reset, suspend/resume;
> this patch adds a test which compares register state before and after
> the test scenario.
>
> This test currently verifies only bdw workarounds.
>
> Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
On top of Thomas' comments about using igt infrastructure some more below.
> ---
> tests/Makefile.sources | 1 +
> tests/gem_workarounds.c | 238 ++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 239 insertions(+)
> create mode 100644 tests/gem_workarounds.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index 0eb9369..a17acd1 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -127,20 +127,21 @@ TESTS_progs = \
> gem_storedw_loop_vebox \
> gem_threaded_access_tiled \
> gem_tiled_fence_blits \
> gem_tiled_pread \
> gem_tiled_pread_pwrite \
> gem_tiled_swapping \
> gem_tiling_max_stride \
> gem_unfence_active_buffers \
> gem_unref_active_buffers \
> gem_wait_render_timeout \
> + gem_workarounds \
> gen3_mixed_blits \
> gen3_render_linear_blits \
> gen3_render_mixed_blits \
> gen3_render_tiledx_blits \
> gen3_render_tiledy_blits \
> gen7_forcewake_mt \
> kms_force_connector \
> kms_sink_crc_basic \
> kms_fence_pin_leak \
> pm_psr \
> diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
> new file mode 100644
> index 0000000..56bf4b1
> --- /dev/null
> +++ b/tests/gem_workarounds.c
> @@ -0,0 +1,238 @@
> +/*
> + * Copyright © 2014 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + * Authors:
> + * Arun Siluvery <arun.siluvery at linux.intel.com>
> + *
> + */
> +
> +#define _GNU_SOURCE
> +#include <stdbool.h>
> +#include <unistd.h>
> +#include <stdlib.h>
> +#include <stdio.h>
> +#include <string.h>
> +#include <fcntl.h>
> +#include <inttypes.h>
> +#include <errno.h>
> +#include <sys/stat.h>
> +#include <sys/ioctl.h>
> +#include <sys/mman.h>
> +#include <time.h>
> +#include <signal.h>
> +
> +#include "ioctl_wrappers.h"
> +#include "drmtest.h"
> +#include "igt_debugfs.h"
> +#include "igt_aux.h"
> +#include "intel_chipset.h"
> +#include "intel_io.h"
> +
> +enum operation {
> + GPU_RESET = 0x01,
> + SUSPEND_RESUME = 0x02,
> +};
> +
> +struct intel_wa_reg {
> + uint32_t addr;
> + uint32_t value;
> + uint32_t mask;
> +};
> +
> +int drm_fd;
> +uint32_t devid;
> +static drm_intel_bufmgr *bufmgr;
> +struct intel_batchbuffer *batch;
> +int num_wa;
> +struct intel_wa_reg *wa_regs;
> +
> +
> +static void test_hang_gpu(void)
> +{
> + int retry_count = 30;
> + enum stop_ring_flags flags;
> + struct drm_i915_gem_execbuffer2 execbuf;
> + struct drm_i915_gem_exec_object2 gem_exec;
> + uint32_t b[2] = {MI_BATCH_BUFFER_END};
> +
> + igt_assert(retry_count);
> + igt_set_stop_rings(STOP_RING_DEFAULTS);
> +
> + memset(&gem_exec, 0, sizeof(gem_exec));
> + gem_exec.handle = gem_create(drm_fd, 4096);
> + gem_write(drm_fd, gem_exec.handle, 0, b, sizeof(b));
> +
> + memset(&execbuf, 0, sizeof(execbuf));
> + execbuf.buffers_ptr = (uintptr_t)&gem_exec;
> + execbuf.buffer_count = 1;
> + execbuf.batch_len = sizeof(b);
> +
> + drmIoctl(drm_fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
> +
> + while(retry_count--) {
> + flags = igt_get_stop_rings();
> + if (flags == 0)
> + break;
> + printf("gpu hang not yet cleared, retries left %d\n", retry_count);
> + sleep(1);
> + }
> +
> + flags = igt_get_stop_rings();
> + if (flags)
> + igt_set_stop_rings(STOP_RING_NONE);
> +}
> +
> +static void test_suspend_resume(void)
> +{
> + printf("Suspending the device ...\n");
> + igt_system_suspend_autoresume();
> +}
> +
> +static void get_current_wa_data(struct intel_wa_reg **curr, int num)
> +{
> + int i;
> + struct intel_wa_reg *ptr = NULL;
> +
> + ptr = *curr;
> +
> + intel_register_access_init(intel_get_pci_device(), 0);
> +
> + for (i = 0; i < num; ++i) {
> + ptr[i].addr = wa_regs[i].addr;
> + ptr[i].value = intel_register_read(wa_regs[i].addr);
> + ptr[i].mask = wa_regs[i].mask;
> + }
> +
> + intel_register_access_fini();
> +}
> +
> +static void check_workarounds(enum operation op, int num)
> +{
> + int i;
> + int fail_count = 0;
> + int status = 0;
> + struct intel_wa_reg *current_wa = NULL;
> +
> + switch (op) {
> + case GPU_RESET:
> + test_hang_gpu();
> + break;
> +
> + case SUSPEND_RESUME:
> + test_suspend_resume();
> + break;
> +
> + default:
> + fail_count = 1;
> + goto out;
> + }
> +
> + current_wa = malloc(num * sizeof(*current_wa));
> + igt_assert(current_wa);
> + get_current_wa_data(¤t_wa, num);
> +
> + printf("Address\tbefore\t\tafter\t\tw/a mask\tresult\n");
> + for (i = 0; i < num; ++i) {
> + status = (current_wa[i].value & current_wa[i].mask) !=
> + (wa_regs[i].value & wa_regs[i].mask);
> + if (status)
> + ++fail_count;
> +
> + printf("0x%X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
> + current_wa[i].addr, wa_regs[i].value,
> + current_wa[i].value, current_wa[i].mask,
> + status ? "fail" : "success");
> + }
> +
> +out:
> + free(current_wa);
> + igt_assert(fail_count == 0);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + igt_subtest_init(argc, argv);
Just use an igt_main block.
> +
> + igt_fixture {
> + int i;
> + int ret;
> + FILE *file;
> + int card_index;
> + const char *dri_path = "/sys/kernel/debug/dri";
> + char *filename = NULL;
> + char *line = NULL;
> + size_t line_size;
> +
> + drm_fd = drm_open_any();
> +
> + bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
> + devid = intel_get_drm_devid(drm_fd);
> + batch = intel_batchbuffer_alloc(bufmgr, devid);
> +
> + card_index = drm_get_card();
> + igt_assert(card_index != -1);
> +
> + ret = asprintf(&filename, "%s/%d/intel_wa_registers",
> + dri_path, card_index);
> + igt_assert(ret > 0);
> +
> + file = fopen(filename, "r");
> + igt_assert(file > 0);
> +
> + ret = getline(&line, &line_size, file);
> + igt_assert(ret > 0);
> + sscanf(line, "Workarounds applied: %d", &num_wa);
> + igt_assert(num_wa > 0);
> +
> + wa_regs = malloc(num_wa * sizeof(*wa_regs));
> +
> + i = 0;
> + while(getline(&line, &line_size, file) > 0) {
> + sscanf(line, "0x%X: 0x%08X, mask: 0x%08X",
> + &wa_regs[i].addr, &wa_regs[i].value,
> + &wa_regs[i].mask);
> + ++i;
> + }
> +
> + free(line);
> + fclose(file);
> + }
> +
> + igt_subtest("check-workaround-data-after-reset") {
> + if (IS_BROADWELL(devid))
> + check_workarounds(GPU_RESET, num_wa);
> + else
> + igt_skip_on("No Workaround table available!!\n");
> + }
> +
> + igt_subtest("check-workaround-data-after-suspend-resume") {
> + if (IS_BROADWELL(devid))
> + check_workarounds(SUSPEND_RESUME, num_wa);
> + else
> + igt_skip_on("No Workaround table available!!\n");
> + }
> +
> + free(wa_regs);
> +
> + close(drm_fd);
The above two need to be in an igt_fixture. Otherwise you break test
enumeration a bit - run the test with <binary> --list-subtests. We
probably need a basic acceptance test for this stuff ...
-Daniel
> + igt_exit();
> +}
> --
> 2.0.4
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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