[Intel-gfx] [PATCH v2] drm/i915: Fix to Enable GT/PM Interrupts for cherryview.

[Daniel Vetter]

On Fri, Aug 22, 2014 at 08:32:40AM +0530, deepak.s at linux.intel.com wrote:
> From: Deepak S <deepak.s at linux.intel.com>
> 
> Programing GT IER interrupts was fumbled while enabling Interrupts for
> gen8
> 
> This is a regression from
>     commit abd58f0175915bed644aa67c8f69dc571b8280e0
>     Author: Ben Widawsky <benjamin.widawsky at intel.com>
>     Date:   Sat Nov 2 21:07:09 2013 -0700
> 
> 	drm/i915/bdw: Implement interrupt changes

_Really_ unlikely that this is a regression from this commit, since that
introduced all the gen8 interrupt handling in the first place. I think
this is because of the reworked interrupt handling over gpu resets, where
we want to keep rps interrupts enabled. But I'm not terribly sure.

I think a more convincing story is that this is an oversight from

commit a6706b45a57a23a613b34793e1414991b60a09c1
Author: Deepak S <deepak.s at linux.intel.com>
Date:   Sat Mar 15 20:23:22 2014 +0530

    drm/i915: Track the enabled PM interrupts in dev_priv

or more precisely (since chv wasn't public back then iirc) we forgot to
add the corresponding patch to -internal.

In any case please clarify the commit message and please also add a few
words about why exactly we need this - I had to dig through git history to
figure this all out.

I've applied the patch already, so you can just reply with the revised
commit message that I should put in.

Thanks, Daniel

> v2: Kill the loop and init GT interrupts (Ville)
> 
> Signed-off-by: Deepak S <deepak.s at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d5445e7..c33cf89 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3799,8 +3799,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  
>  static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
>  {
> -	int i;
> -
>  	/* These are interrupts we'll toggle with the ring mask register */
>  	uint32_t gt_interrupts[] = {
>  		GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> @@ -3817,10 +3815,11 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
>  			GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
>  		};
>  
> -	for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
> -		GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
> -
>  	dev_priv->pm_irq_mask = 0xffffffff;
> +	GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
> +	GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
> +	GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, dev_priv->pm_rps_events);
> +	GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
>  }
>  
>  static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch