[Intel-gfx] [PATCH] drm/i915/bdw: Let the memory controller do all the swizzling

[Daniel Vetter]

On Wed, Aug 27, 2014 at 11:51:59AM +0100, Damien Lespiau wrote:
> Previously, it was possible for the GPU memory accesses to be swizzled
> to try to optimize the fetches for tiled buffers. This swizzling was on
> top of what the memory controller in the uncore already does.
> 
> With broadwell, we drop that GPU side swizzling, and the corresponding
> initialization in 3 units (GAM, GT, DE). All those bits are reserved, as
> specs put it:
> 
>   Before Gen8, there was a historical configuration control field to
>   swizzle address bit[6] for in X/Y tiling modes. This was set in three
>   different places: TILECTL[1:0], ARB_MODE[5:4], and
>   DISP_ARB_CTL[14:13]"
> 
>   For Gen8 the swizzle fields are all reserved, and the CPU's memory
>   controller performs all address swizzling modifications.
> 
> This also means that user space doesn't have to manually swizzle when
> accessing tiled buffers from the CPU, and so we always return
> I915_BIT_6_SWIZZLE_NONE from i915_gem_detect_bit_6_swizzle(), which
> short-circuits the initialization of the registers mentionned above in
> i915_gem_init_swizzling().
> 
> v2: Refine the explanation a bit more (Daniel)
> v3: Make it BDW+ specific (Steve)
> 
> Cc: Steve Aarnio <steve.j.aarnio at linux.intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c        | 2 --
>  drivers/gpu/drm/i915/i915_gem_tiling.c | 9 ++++++++-
>  drivers/gpu/drm/i915/i915_reg.h        | 1 -
>  3 files changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 60b8bd1..37a45aa 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4641,8 +4641,6 @@ void i915_gem_init_swizzling(struct drm_device *dev)
>  		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>  	else if (IS_GEN7(dev))
>  		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> -	else if (IS_GEN8(dev))
> -		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));

I didn't that much point in dropping this, just in case some bios escaped
that uses this. And we'd need to perfectly copy the swizzle mode for
fastboot.

We can ditch it once bdw is shipping I guess, but otoh this won't really
ever hurt.

Queued for -next, thanks for the patch.
-Daniel

>  	else
>  		BUG();
>  }
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index 7e623bf..2cefb59 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -91,7 +91,14 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
>  	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>  	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>  
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
> +		/*
> +		 * On BDW+, swizzling is not used. We leave the CPU memory
> +		 * controller in charge of optimizing memory accesses without
> +		 * the extra address manipulation GPU side.
> +		 *
> +		 * VLV and CHV don't have GPU swizzling.
> +		 */
>  		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
>  		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
>  	} else if (INTEL_INFO(dev)->gen >= 6) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 82414b8..16fde02 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1071,7 +1071,6 @@ enum punit_power_well {
>  
>  #define GAMTARBMODE		0x04a08
>  #define   ARB_MODE_BWGTLB_DISABLE (1<<9)
> -#define   ARB_MODE_SWIZZLE_BDW	(1<<1)
>  #define RENDER_HWS_PGA_GEN7	(0x04080)
>  #define RING_FAULT_REG(ring)	(0x4094 + 0x100*(ring)->id)
>  #define   RING_FAULT_GTTSEL_MASK (1<<11)
> -- 
> 1.8.3.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch