[Intel-gfx] [PATCH 6/9] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

[Jani Nikula]

On Sat, 29 Nov 2014, Gaurav K Singh <gaurav.k.singh at intel.com> wrote:
> For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.
>
> v2: Address review comments by Jani
>     - Added wait time for PLL to be locked.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh at intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |    9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index fa7a6ca..93d8e9a 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>  
>  	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>  
> +	if (intel_dsi->dual_link)
> +		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
> +
>  	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
>  		      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
>  
> @@ -269,12 +272,12 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
>  	tmp |= DSI_PLL_VCO_EN;
>  	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
>  
> -	mutex_unlock(&dev_priv->dpio_lock);
> -
> -	if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
> +	if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
> +					DSI_PLL_LOCK, 20)) {
>  		DRM_ERROR("DSI PLL lock failed\n");
>  		return;
>  	}
> +	mutex_unlock(&dev_priv->dpio_lock);

This hunk seems to be an unrelated change, I think it should be a
separate patch.

BR,
Jani.

>  
>  	DRM_DEBUG_KMS("DSI PLL locked\n");
>  }
> -- 
> 1.7.9.5
>
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-- 
Jani Nikula, Intel Open Source Technology Center