[Intel-gfx] [PATCH] drm/i915/chv: Add additional workarounds for CHV

[Ville Syrjälä]

On Wed, Dec 03, 2014 at 07:15:31PM +0000, Arun Siluvery wrote:
> These w/a were recently identified while debugging another issue,
> +WaClearFlowControlGpgpuContextSave:chv
> +Wa4x4STCOptimizationDisable:chv
> 
> For: VIZ-4090
> Change-Id: I08d2176dec609396c3a7c2e48b2413e233799fc4
> Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc03fac..7c7663f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6131,6 +6131,7 @@ enum punit_power_well {
>  #define   GEN9_DG_MIRROR_FIX_ENABLE	(1<<5)
>  
>  #define GEN8_ROW_CHICKEN		0xe4f0
> +#define   FLOW_CONTROL_ENABLE		(1<<15)
>  #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
>  #define   STALL_DOP_GATING_DISABLE		(1<<5)
>  
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 79b4ca5..525c9bf 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -796,8 +796,10 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>  
>  	/* WaDisablePartialInstShootdown:chv */
>  	/* WaDisableThreadStallDopClockGating:chv */
> +	/* WaClearFlowControlGpgpuContextSave:chv */
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>  			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
> +			  FLOW_CONTROL_ENABLE |

This seems to be the default value already. I suppose there's no real
harm in setting it though, but then we should also do the same for BDW.

Would be nice if we actually did a GPU reset on driver load to guarantee
a more consistent initial state...

>  			  STALL_DOP_GATING_DISABLE);
>  
>  	/* Use Force Non-Coherent whenever executing a 3D context. This is a
> @@ -810,6 +812,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>  			  HDC_FORCE_NON_COHERENT |
>  			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);
>  
> +	/* Wa4x4STCOptimizationDisable:chv */
> +	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
> +
>  	return 0;
>  }
>  
> -- 
> 2.1.2
> 
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-- 
Ville Syrjälä
Intel OTC