[Intel-gfx] [PATCH v2 2/2] drm/i915: sanitize RPS resetting during GPU reset

[Imre Deak]

On Thu, 2014-12-04 at 14:58 +0100, Daniel Vetter wrote:
> On Thu, Dec 04, 2014 at 02:59:32PM +0200, Imre Deak wrote:
> > Atm, we don't disable RPS interrupts and related work items before
> > resetting the GPU. This may interfere with the following GPU
> > initialization and cause RPS interrupts to show up in PM_IIR too early
> > before calling gen6_enable_rps_interrupts() (triggering a WARN there).
> > 
> > Solve this by disabling RPS interrupts and flushing any related work
> > items before resetting the GPU.
> > 
> > v2:
> > - split out the common parts of the gt suspend and the new gt reset
> >   functions (Paulo)
> > 
> > Reported-by: He, Shuang <shuang.he at intel.com>
> > Testcase: igt/gem_reset_stats/ban-render
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86644
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c |  5 ++++-
> >  drivers/gpu/drm/i915/intel_pm.c | 28 +++++++++++++++++++---------
> >  2 files changed, 23 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 71be3c9..8377249 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -810,6 +810,9 @@ int i915_reset(struct drm_device *dev)
> >  	if (!i915.reset)
> >  		return 0;
> >  
> > +	if (drm_core_check_feature(dev, DRIVER_MODESET))
> > +		intel_reset_gt_powersave(dev);
> 
> UMS support is dead, so you can leave this hunk out.

Ok, we can call here intel_reset_gt_powersave() unconditionally.

> -Daniel
> 
> > +
> >  	mutex_lock(&dev->struct_mutex);
> >  
> >  	i915_gem_reset(dev);
> > @@ -881,7 +884,7 @@ int i915_reset(struct drm_device *dev)
> >  		 * of re-init after reset.
> >  		 */
> >  		if (INTEL_INFO(dev)->gen > 5)
> > -			intel_reset_gt_powersave(dev);
> > +			intel_enable_gt_powersave(dev);
> >  	} else {
> >  		mutex_unlock(&dev->struct_mutex);
> >  	}
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 78911e2..45c786f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6072,6 +6072,20 @@ void intel_cleanup_gt_powersave(struct drm_device *dev)
> >  		valleyview_cleanup_gt_powersave(dev);
> >  }
> >  
> > +static void gen6_suspend_rps(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > +	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> > +
> > +	/*
> > +	 * TODO: disable RPS interrupts on GEN9+ too once RPS support
> > +	 * is added for it.
> > +	 */
> > +	if (INTEL_INFO(dev)->gen < 9)
> > +		gen6_disable_rps_interrupts(dev);
> > +}
> > +
> >  /**
> >   * intel_suspend_gt_powersave - suspend PM work and helper threads
> >   * @dev: drm device
> > @@ -6087,14 +6101,7 @@ void intel_suspend_gt_powersave(struct drm_device *dev)
> >  	if (INTEL_INFO(dev)->gen < 6)
> >  		return;
> >  
> > -	flush_delayed_work(&dev_priv->rps.delayed_resume_work);
> > -
> > -	/*
> > -	 * TODO: disable RPS interrupts on GEN9+ too once RPS support
> > -	 * is added for it.
> > -	 */
> > -	if (INTEL_INFO(dev)->gen < 9)
> > -		gen6_disable_rps_interrupts(dev);
> > +	gen6_suspend_rps(dev);
> >  
> >  	/* Force GPU to min freq during suspend */
> >  	gen6_rps_idle(dev_priv);
> > @@ -6197,8 +6204,11 @@ void intel_reset_gt_powersave(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > +	if (INTEL_INFO(dev)->gen < 6)
> > +		return;
> > +
> > +	gen6_suspend_rps(dev);
> >  	dev_priv->rps.enabled = false;
> > -	intel_enable_gt_powersave(dev);
> >  }
> >  
> >  static void ibx_init_clock_gating(struct drm_device *dev)
> > -- 
> > 1.8.4
> > 
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