[Intel-gfx] [PATCH] drm/i915/bdw: Fix the write setting up the WIZ hashing mode

[Damien Lespiau]

On Mon, Dec 08, 2014 at 03:23:49PM +0100, Daniel Vetter wrote:
> > #define _MASKED_BIT_ENABLE(a) _MASKED_FIELD(a, a)
> > #define _MASKED_BIT_DISABLE(a) _MASKED_FIELD(a, 0)
> 
> Ok and I right away screwed up the argument ordering in the DISABLE one
> because the bits we set are before the mask. All the bitmasking functions
> we have in e.g. i915_irq.c ilk_update_gt_irq so for consistency I think we
> should flip it in this one here, too. Otherwise that bit of inconsistency
> will trip up tons of people in the future.
> 
> Jani, can you please apply that fixup if Damien acks it?

(for the record ack'ed)

-- 
Damien