[Intel-gfx] [PATCH] drm/i915/bdw: Fix the write setting up the WIZ hashing mode

[Damien Lespiau]

On Mon, Dec 08, 2014 at 02:17:45PM +0000, Dave Gordon wrote:
> On 08/12/14 13:59, Damien Lespiau wrote:
> > On Mon, Dec 08, 2014 at 02:33:57PM +0200, Jani Nikula wrote:
> >>>  #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
> >>>  #define _MASKED_BIT_DISABLE(a) ((a) << 16)
> >>> +#define _MASKED_FIELD(value, mask) (((mask) << 16) | (value))
> >>
> >> Obligatory bikeshed, wouldn't you say _MASKED_BIT_{ENABLE,DISABLE} are
> >> special cases of _MASKED_FIELD...? ;)
> > 
> > That's because we're not just enabling or disabling bits here but
> > setting a multi-bits value.
> > 
> >   _MASKED_FIELD(2 << 4, 0x3 << 4);
> > 
> 
> So you could
> 
> #define	__MASKED_BIT_DISABLE(a)		(__MASKED_FIELD(0, (a)))
> #define	__MASKED_BIT_ENABLE(a)		(__MASKED_FIELD((a), (a)))
> 
> which I think is what Jani was referring to ...
> 
> Bikeshed++: do we care about the double evaluation of (a) in these macros?

Oh of course, misread that. We could also avoid the double evaluation
indeed and chris suggests (on IRC) BUILD_BUG_ON(bit & ~mask); (super
good!)

-- 
Damien