[Intel-gfx] [PATCH] drm/i915: Add MI_SET_APPID cmd to cmd parser tables

[Bloomfield, Jon]

> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces at lists.freedesktop.org] On Behalf
> Of michael.h.nguyen at intel.com
> Sent: Friday, November 21, 2014 5:36 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: Vetter, Daniel; Barnes, Jesse
> Subject: [Intel-gfx] [PATCH] drm/i915: Add MI_SET_APPID cmd to cmd parser
> tables
> 
> From: "Michael H. Nguyen" <michael.h.nguyen at intel.com>
> 
> Was missing
> 
> Issue: VIZ-4701
> Signed-off-by: Michael H. Nguyen <michael.h.nguyen at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 14 +++++++++++---
>  drivers/gpu/drm/i915/i915_reg.h        |  3 +++
>  2 files changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c
> b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 22c992a..364aff7 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -152,6 +152,7 @@ static const struct drm_i915_cmd_descriptor
> render_cmds[] = {
>  	CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
>  	CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
>  	CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
> +	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
>  	CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
>  	CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
>  	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3F,   B,
> @@ -210,6 +211,7 @@ static const struct drm_i915_cmd_descriptor
> hsw_render_cmds[] = {
>  	CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
>  	CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
>  	CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
> +	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
>  	CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
>  	CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
>  	CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
> @@ -229,6 +231,7 @@ static const struct drm_i915_cmd_descriptor
> hsw_render_cmds[] = {
> 
>  static const struct drm_i915_cmd_descriptor video_cmds[] = {
>  	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
> +	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
>  	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
>  	      .bits = {{
>  			.offset = 0,
> @@ -272,6 +275,7 @@ static const struct drm_i915_cmd_descriptor
> video_cmds[] = {
> 
>  static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
>  	CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
> +	CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
>  	CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
>  	      .bits = {{
>  			.offset = 0,
> @@ -481,13 +485,17 @@ static u32 gen7_bsd_get_cmd_length_mask(u32
> cmd_header)
>  	u32 client = (cmd_header & INSTR_CLIENT_MASK) >>
> INSTR_CLIENT_SHIFT;
>  	u32 subclient =
>  		(cmd_header & INSTR_SUBCLIENT_MASK) >>
> INSTR_SUBCLIENT_SHIFT;
> +	u32 op = (cmd_header & INSTR_26_TO_24_MASK) >>
> INSTR_26_TO_24_SHIFT;
> 
>  	if (client == INSTR_MI_CLIENT)
>  		return 0x3F;
>  	else if (client == INSTR_RC_CLIENT) {
> -		if (subclient == INSTR_MEDIA_SUBCLIENT)
> -			return 0xFFF;
> -		else
> +		if (subclient == INSTR_MEDIA_SUBCLIENT) {
> +			if (op == 6)
> +				return 0xFFFF;
> +			else
> +				return 0xFFF;
> +		} else
>  			return 0xFF;
>  	}
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 7a77cd5..c881d88 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -204,6 +204,8 @@
>  #define INSTR_SUBCLIENT_SHIFT   27
>  #define INSTR_SUBCLIENT_MASK    0x18000000
>  #define   INSTR_MEDIA_SUBCLIENT 0x2
> +#define INSTR_26_TO_24_MASK	0x7000000
> +#define   INSTR_26_TO_24_SHIFT	24
> 
>  /*
>   * Memory interface instructions used by the kernel @@ -233,6 +235,7 @@
>  #define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
>  #define MI_SUSPEND_FLUSH	MI_INSTR(0x0b, 0)
>  #define   MI_SUSPEND_FLUSH_EN	(1<<0)
> +#define MI_SET_APPID		MI_INSTR(0x0e, 0)
>  #define MI_OVERLAY_FLIP		MI_INSTR(0x11, 0)
>  #define   MI_OVERLAY_CONTINUE	(0x0<<21)
>  #define   MI_OVERLAY_ON		(0x1<<21)

Reviewed-by: Jon Bloomfield <jon.bloomfield at intel.com>

> --
> 1.9.1
> 
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