[Intel-gfx] [PATCH 1/2] drm/i915: Infrastructure for supporting different GGTT views per object
Michel Thierry
michel.thierry at intel.com
Thu Dec 11 02:18:12 PST 2014
On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>
> Things like reliable GGTT mappings and mirrored 2d-on-3d display will need
> to map objects into the same address space multiple times.
>
> Added a GGTT view concept and linked it with the VMA to distinguish between
> multiple instances per address space.
>
> New objects and GEM functions which do not take this new view as a parameter
> assume the default of zero (I915_GGTT_VIEW_NORMAL) which preserves the
> previous behaviour.
>
> This now means that objects can have multiple VMA entries so the code which
> assumed there will only be one also had to be modified.
>
> Alternative GGTT views are supposed to borrow DMA addresses from obj->pages
> which is DMA mapped on first VMA instantiation and unmapped on the last one
> going away.
>
> v2:
> * Removed per view special casing in i915_gem_ggtt_prepare /
> finish_object in favour of creating and destroying DMA mappings
> on first VMA instantiation and last VMA destruction. (Daniel Vetter)
> * Simplified i915_vma_unbind which does not need to count the GGTT views.
> (Daniel Vetter)
> * Also moved obj->map_and_fenceable reset under the same check.
> * Checkpatch cleanups.
>
> v3:
> * Only retire objects once the last VMA is unbound.
>
> v4:
> * Keep scatter-gather table for alternative views persistent for the
> lifetime of the VMA.
> * Propagate binding errors to callers and handle appropriately.
>
> v5:
> * Explicitly look for normal GGTT view in i915_gem_obj_bound to align
> usage in i915_gem_object_ggtt_unpin. (Michel Thierry)
> * Change to single if statement in i915_gem_obj_to_ggtt. (Michel Thierry)
> * Removed stray semi-colon in i915_gem_object_set_cache_level.
>
> For: VIZ-4544
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Good catch in i915_gem_object_set_cache_level.
Reviewed-by: Michel Thierry <michel.thierry at intel.com>
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