[Intel-gfx] [PATCH 2/4] drm/i915/chv: Populate total EU count on Cherryview

[Deepak S]

On Thursday 11 December 2014 05:39 PM, Jani Nikula wrote:
> On Fri, 12 Dec 2014, deepak.s at linux.intel.com wrote:
>> From: Deepak S <deepak.s at linux.intel.com>
>>
>> Starting with Cherryview, devices may have a varying number of EU for
>> a given ID due to creative fusing. Punit support different frequency for
>> different fuse data. We use this patch to help get total eu enabled and
>> read the right offset to get RP0
>>
>> Based upon a patch from Jeff, but reworked to only store eu_total and
>> avoid sending info to userspace
>>
>> Signed-off-by: Deepak S <deepak.s at linux.intel.com>
>> Signed-off-by: Jeff McGee <jeff.mcgee at intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_dma.c | 11 +++++++++++
>>   drivers/gpu/drm/i915/i915_drv.h |  1 +
>>   drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
>>   3 files changed, 23 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>> index 887d88f..2bd36b6 100644
>> --- a/drivers/gpu/drm/i915/i915_dma.c
>> +++ b/drivers/gpu/drm/i915/i915_dma.c
>> @@ -598,6 +598,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>>   			info->num_pipes = 0;
>>   		}
>>   	}
>> +
>> +	if (IS_CHERRYVIEW(dev)) {
>> +		u32 fuse, mask_eu;
>> +
>> +		fuse = I915_READ(CHV_FUSE_GT);
>> +		mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
>> +				  CHV_FGT_EU_DIS_SS0_R1_MASK |
>> +				  CHV_FGT_EU_DIS_SS1_R0_MASK |
>> +				  CHV_FGT_EU_DIS_SS1_R1_MASK);
>> +		info->eu_total = 16 - hweight32(mask_eu);
>> +	}
>>   }
>>   
>>   /**
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 9381504..b58bad4 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -624,6 +624,7 @@ struct intel_device_info {
>>   	int trans_offsets[I915_MAX_TRANSCODERS];
>>   	int palette_offsets[I915_MAX_PIPES];
>>   	int cursor_offsets[I915_MAX_PIPES];
>> +	unsigned int eu_total;
>>   };
>>   
>>   #undef DEFINE_FLAG
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 93fdad8..b57cba3 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1466,6 +1466,17 @@ enum punit_power_well {
>>   #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)
>>   #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1<<10)
>>   
>> +/* Fuse readout registers for GT */
>> +#define CHV_FUSE_GT			0x182168
> Should this be (VLV_DISPLAY_BASE + 0x2168)?
>   
>> +#define   CHV_FGT_EU_DIS_SS0_R0_SHIFT	16
>> +#define   CHV_FGT_EU_DIS_SS0_R0_MASK	(0xf<<CHV_FGT_EU_DIS_SS0_R0_SHIFT)
>> +#define   CHV_FGT_EU_DIS_SS0_R1_SHIFT	20
>> +#define   CHV_FGT_EU_DIS_SS0_R1_MASK	(0xf<<CHV_FGT_EU_DIS_SS0_R1_SHIFT)
>> +#define   CHV_FGT_EU_DIS_SS1_R0_SHIFT	24
>> +#define   CHV_FGT_EU_DIS_SS1_R0_MASK	(0xf<<CHV_FGT_EU_DIS_SS1_R0_SHIFT)
>> +#define   CHV_FGT_EU_DIS_SS1_R1_SHIFT	28
>> +#define   CHV_FGT_EU_DIS_SS1_R1_MASK	(0xf<<CHV_FGT_EU_DIS_SS1_R1_SHIFT)
> Please add spaces both sides of "<<" if you end up sending a v2.

Thanks for review.
I will address both the comment and send v2

>> +
>>   #define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050
>>   #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>>   #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
>> -- 
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx