[Intel-gfx] [PATCH] drm/i915/skl: Correcting the flushing of pipe

[sonika.jindal at intel.com]

From: Sonika Jindal <sonika.jindal at intel.com>

We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.

Signed-off-by: Sonika Jindal <sonika.jindal at intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |    3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5748bf9..8cd045a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3633,9 +3633,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
 		    skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
 			skl_wm_flush_pipe(dev_priv, pipe, 2);
 			intel_wait_for_vblank(dev, pipe);
+			reallocated[pipe] = true;
 		}
-
-		reallocated[pipe] = true;
 	}
 
 	/*
-- 
1.7.10.4