[Intel-gfx] [PATCH 2/3] drm/i915: Force the CS stall for invalidate flushes

[Ville Syrjälä]

On Thu, Dec 11, 2014 at 08:17:00AM +0000, Chris Wilson wrote:
> In order to act as a full command barrier by itself, we need to tell the
> pipecontrol to actually stall the command streamer while the flush runs.
> We require the full command barrier before operations like
> MI_SET_CONTEXT, which currently rely on a prior invalidate flush.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=83677
> Cc: Simon Farnsworth <simon at farnz.org.uk>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: stable at vger.kernel.org
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 282279b83ca4..02fb478a2867 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -380,6 +380,8 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
>  		flags |= PIPE_CONTROL_QW_WRITE;
>  		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
>  
> +		flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
> +

Hmm. BSpec says that the render cache won't be flushed when this bit
is set. Is that going to cause problems for the gpu_cache_dirty cases
where seem to do invalidate+flush with a single PIPE_CONTROL?

>  		/* Workaround: we must issue a pipe_control with CS-stall bit
>  		 * set before a pipe_control command that has the state cache
>  		 * invalidate bit set. */
> -- 
> 2.1.3
> 
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-- 
Ville Syrjälä
Intel OTC