[Intel-gfx] [PATCH v3 3/8] drm/i915: Partition the fence registers for vGPU in i915 driver

[Tvrtko Ursulin]

On 11/13/2014 12:02 PM, Yu Zhang wrote:
> With Intel GVT-g, the fence registers are partitioned by multiple
> vGPU instances in different VMs. Routine i915_gem_load() is modified
> to reset the num_fence_regs, when the driver detects it's running in
> a VM. And the allocated fence number is provided in PV INFO page
> structure.
>
> Signed-off-by: Yu Zhang <yu.c.zhang at linux.intel.com>
> Signed-off-by: Jike Song <jike.song at intel.com>
> Signed-off-by: Eddie Dong <eddie.dong at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem.c | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 1de94cc..0c8b32e 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -29,6 +29,7 @@
>   #include <drm/drm_vma_manager.h>
>   #include <drm/i915_drm.h>
>   #include "i915_drv.h"
> +#include "i915_vgpu.h"
>   #include "i915_trace.h"
>   #include "intel_drv.h"
>   #include <linux/oom.h>
> @@ -5014,6 +5015,10 @@ i915_gem_load(struct drm_device *dev)
>   	else
>   		dev_priv->num_fence_regs = 8;
>
> +	if (intel_vgpu_active(dev))
> +		dev_priv->num_fence_regs =
> +				I915_READ(vgtif_reg(avail_rs.fence_num));
> +
>   	/* Initialize fence registers to zero */
>   	INIT_LIST_HEAD(&dev_priv->mm.fence_list);
>   	i915_gem_restore_fences(dev);
>

You don't need a start offset and number of allocated fences per domain?

Regards,

Tvrtko