[Intel-gfx] [PATCH] drm/i915: use TAIL rather than ACTHD for synchronising reads

[Dave Gordon]

On some generations of chips, it is necessary to read an MMIO register
before getting the sequence number from the status page in main memory,
in order to ensure coherency; and on all generations this should be
either helpful or harmless.

In general, we want this operation to be the cheapest possible, since
we require only the side-effect of DMA completion and don't interpret
the result of the read, and don't require any coordination with other
threads, power domains, or anything else.

However, finding a suitable register may be problematic; on GEN6 chips
the ACTHD register was used, but on VLV et al access to this register
requires FORCEWAKE and therefore many complications involving spinlocks
and polling.

So this commit introduces this synchronising operation as a distinct
vfunc in uncore, so that it can be GEN- or chip-specific if needed.

For now, a sample 'universal' implementation is provided which just
reads the TAIL register of the render engine, this being a register
which should always be accessible on all GENs without requiring
forcewake or other complications.

We then change gen6_ring_get_seqno() to use this new SYNC_READ rather
than a POSTING_READ of ACTHD. Note that both older (pre-GEN6) and newer
(GEN8+) devices don't currently include any posting read in their own
get_seqno() implementations, so this affects only GEN6 and 7 devices.

Signed-off-by: Dave Gordon <david.s.gordon at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |    7 +++++++
 drivers/gpu/drm/i915/intel_ringbuffer.c |    2 +-
 drivers/gpu/drm/i915/intel_uncore.c     |    9 +++++++++
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3047291f..9826cb6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -593,6 +593,9 @@ struct intel_uncore_funcs {
 				uint32_t val, bool trace);
 	void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
 				uint64_t val, bool trace);
+
+	/* Read any suitable register, for DMA synchronisation purposes only */
+	void (*sync_read)(struct drm_i915_private *dev_priv);
 };
 
 struct intel_uncore {
@@ -3161,6 +3164,8 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
 #define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
 #define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
 
+#define I915_SYNC_READ()	dev_priv->uncore.funcs.sync_read(dev_priv)
+
 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
  * will be implemented using 2 32-bit writes in an arbitrary order with
  * an arbitrary delay between them. This can cause the hardware to
@@ -3184,6 +3189,8 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
 #define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
 #define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)
 
+#define SYNC_READ()		I915_SYNC_READ()
+
 /* "Broadcast RGB" property */
 #define INTEL_BROADCAST_RGB_AUTO 0
 #define INTEL_BROADCAST_RGB_FULL 1
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 12a36f0..74bffce 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1217,7 +1217,7 @@ gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
 	 * ACTHD) before reading the status page. */
 	if (!lazy_coherency) {
 		struct drm_i915_private *dev_priv = ring->dev->dev_private;
-		POSTING_READ(RING_ACTHD(ring->mmio_base));
+		SYNC_READ();
 	}
 
 	return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e9561de..8fc40c4 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -737,6 +737,14 @@ hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
 	}
 }
 
+static void
+gen4_sync_read(struct drm_i915_private *dev_priv)
+{
+	/* No HEADER, no FOOTER, just the raw read */
+	(void)__raw_i915_read32(dev_priv,
+				RING_TAIL(dev_priv->ring[RCS].mmio_base));
+}
+
 #define REG_READ_HEADER(x) \
 	unsigned long irqflags; \
 	u##x val = 0; \
@@ -1139,6 +1147,7 @@ do { \
 	dev_priv->uncore.funcs.mmio_readw = x##_read16; \
 	dev_priv->uncore.funcs.mmio_readl = x##_read32; \
 	dev_priv->uncore.funcs.mmio_readq = x##_read64; \
+	dev_priv->uncore.funcs.sync_read = gen4_sync_read; \
 } while (0)
 
 void intel_uncore_init(struct drm_device *dev)
-- 
1.7.9.5