[Intel-gfx] [PATCH] drm/i915/hsw: Implement Selective Write workaround

[Chris Wilson]

On Fri, Dec 19, 2014 at 09:26:01AM -0800, Ben Widawsky wrote:
> On Fri, Dec 19, 2014 at 08:20:04AM +0000, Chris Wilson wrote:
> > On Thu, Dec 18, 2014 at 06:20:18PM -0800, Ben Widawsky wrote:
> > > From: Ben Widawsky <ben at bwidawsk.net>
> > > 
> > > The docs specify this needs to be set on HSW GT1 parts. I've implemented it as
> > > such since it should only be needed when using RC6, but it can probably go
> > > anywhere.
> > > 
> > > This patch fixes extremely reproducible hangs on our Jenkins setup.
> > > 
> > > The interesting failure signature is:
> > >   IPEHR: 0x780c0000 (3DSTATE_VF)
> > >   INSTDONE_0: 0xffdfbffa (SVG + VS)
> > 
> > We see the same bug on IVB, and the bug (verified on hsw gt1) persists with i915.enable_rc6=0.
> > -Chris
> 
> I would claim it's not the same bug on IVB. The workaround very specifically
> says HSW GT1 only. The failure signature itself is pretty generic, it just
> suggests the VS went off and did something stupid, and the VF was unable to fill
> the URB. (That's just my best guess) I do apologize if I inadvertently made a
> connection to the IVB bug issue.

The failure message matches the context hang bug: "dies on last
instruction in the context restore" and probably has nothing to do with
the VS.
 
> So, what is your point? I'm willing to concede we don't know all the facts, but
> the [previous version of this] patch demonstrably fixes hangs on HSW GT1.

Just a patch a few days ago that to fix a very ontologically similar bug
for ivb+.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre