[Intel-gfx] [PATCH 1/7] drm/i915: Fix SNB GT_MODE register setup

[Chris Wilson]

On Wed, Feb 05, 2014 at 11:27:31AM +0200, Ville Syrjälä wrote:
> On Tue, Feb 04, 2014 at 09:23:06PM +0000, Chris Wilson wrote:
> > On Tue, Feb 04, 2014 at 09:59:15PM +0200, ville.syrjala at linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > 
> > > On SNB we set up WaSetupGtModeTdRowDispatch:snb early in
> > > gen6_init_clock_gating(). That sets a bit in the GEN6_GT_MODE register.
> > > However later we go and disable all the bits in the same register. And
> > > then we go on to set some other bit. So apparently we never actually
> > > implemented this workaround since the "disable all bits" part was there
> > > already before the w/a got supposedly implemented.
> > > 
> > > These are the relevant commits:
> > > 
> > >  commit 6547fbdbfff62c99e4f7b4f985ff8b3454f33b0f
> > >  Author: Daniel Vetter <daniel.vetter at ffwll.ch>
> > >  Date:   Fri Dec 14 23:38:29 2012 +0100
> > > 
> > >     drm/i915: Implement WaSetupGtModeTdRowDispatch
> > > 
> > >  commit f8f2ac9a76b0f80a6763ca316116a7bab8486997
> > >  Author: Ben Widawsky <ben at bwidawsk.net>
> > >  Date:   Wed Oct 3 19:34:24 2012 -0700
> > > 
> > >     drm/i915: Fix GT_MODE default value
> > > 
> > > So, let's drop the "disable all bits" part, move both writes to
> > > closer proxomity to each other, and name the WIZ hashing bits
> > > appropriately. BSpec is still a bit confused how the bits should
> > > actually be interpreted, but I took the the description for the
> > > high bit since the low bit part only lists values for a single bit.
> > > 
> > > Also add a comment about our choice of WIZ hashing mode.
> > 
> > Changing WiZ hashing mode changes the valid number of threads and
> > userspace assumes best case (WiZ disabled). Worst case we start hanging
> > the chip.
> > 
> > I have no idea how relevant that piece of lore from the spec is, but it
> > something to be wary of when making these changes.
> 
> The thread numbers seem to depend only on the WIZ hashing disable bit.
> I'm not touching that one.

That's ok then. Can I ask that we have a comment next to the WIZ setup
noting userspace's dependence on the WIZ-disable bit?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre