[Intel-gfx] [PATCH] drm/i915/vlv: Added write-enable pte bit support

[Eric Anholt]

akash.goel at intel.com writes:

> From: Akash Goel <akash.goel at intel.com>
>
> This adds support for using the write-enable bit in the GTT entry for VLV.
> This is handled via a read-only flag in the GEM buffer object which
> is then used to check if the write-enable bit has to be set or not
> when writing the GTT entries.
> Currently by default only the Batch buffer & Ring buffers are being marked
> as read only.

What happens when we GTT-mapped write a batchbuffer that had previously
been silently made RO by the kernel?  Does the CPU take a fault?
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