[Intel-gfx] [PATCH 4/9] drm/i915/bdw: Use centralized rc6 info print

[S, Deepak]

On Wed, Jan 29, 2014 at 9:55 AM, Ben Widawsky
> <benjamin.widawsky at intel.com <mailto:benjamin.widawsky at intel.com>> wrote:
>
>     Signed-off-by: Ben Widawsky <ben at bwidawsk.net <mailto:ben at bwidawsk.net>>
>     ---
>       drivers/gpu/drm/i915/intel_pm.c | 6 +++---
>       1 file changed, 3 insertions(+), 3 deletions(-)
>
>     diff --git a/drivers/gpu/drm/i915/intel_pm.c
>     b/drivers/gpu/drm/i915/intel_pm.c
>     index 944b99c..6acb429 100644
>     --- a/drivers/gpu/drm/i915/intel_pm.c
>     +++ b/drivers/gpu/drm/i915/intel_pm.c
>     @@ -3215,10 +3215,10 @@ static void gen8_enable_rps(struct
>     drm_device *dev)
>              /* 3: Enable RC6 */
>              if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
>                      rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>     -       DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
>     "on" : "off");
>     +       intel_print_rc6_info(dev, rc6_mask);
>              I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
>     -                       GEN6_RC_CTL_EI_MODE(1) |
>     -                       rc6_mask);
>     +                                   GEN6_RC_CTL_EI_MODE(1) |
>     +                                   rc6_mask);
>
>              /* 4 Program defaults and thresholds for RPS*/
>              I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request
>     500 MHz */
>     --
>     1.8.5.3
>
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>
Reviewed-by: Deepak S <deepak.s at intel.com>