[Intel-gfx] [PATCH v2 3/3] drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB

[Chris Wilson]

On Tue, Feb 11, 2014 at 05:50:05PM +0200, Ville Syrjälä wrote:
> On Tue, Feb 11, 2014 at 02:14:28PM +0000, Chris Wilson wrote:
> > On Tue, Feb 11, 2014 at 03:55:50PM +0200, ville.syrjala at linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > 
> > > According to BSpec the entire MI_DISPLAY_FLIP packet must be contained
> > > in a single cacheline. Make sure that happens.
> > > 
> > > v2: Use intel_ring_begin_cacheline_safe()
> > 
> > Ugh, no. Let's not make intel_ring_begin() any more complicated and just
> > introduce a function to align the current head in the ringbuffer to a
> > cacheline. Especially with such an interface that is hard to get right.
> 
> This doesn't make intel_ring_begin() itself more complicated, but I
> guess you meant that the new special version is too complicated for
> your taste?

Yes. But it also raises the question of whether I want to use
intel_ring_begin() or intel_ring_begin_safe() everytime I touch the
ring. The slight loss of efficiency is well worth the clarity of
saying:
  ring_align();
  ring_begin()
for those special cases.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre