[Intel-gfx] [PATCH 00/11] [v2] BDW RPS + RC6 + rps fixlets

[Ben Widawsky]

Here is the v2 of the RC6, and RPS enabling for Broadwell. With the last
patch in the series RC6 works without hangs (in limited testing).
Without the last patch, the first batch seems to always hang. I don't
think there any actual fixes over the last version. I changed enough of
the RPS code to not feel comfortable putting Rodrigo's r-b back on.

I had a couple of small tweaks requested by Rodrigo which should be in
there. If they aren't in there, it was a mistake.

Summary:
1-5: All new cleanups new the RPS code.
6: Still in flux default nominal state
7: Pull Jeff's earlier fix around reset into gen8 with a cleanup
8-9: Enable RPS
10-11: Enable RC6

Thanks to Ken for giving this a quick test and allowing me to work from
home :-)


Ben Widawsky (11):
  drm/i915: Reorganize the overclock code
  drm/i915: Fix coding style for RPS
  drm/i915: Rename and comment all the RPS *stuff*
  drm/i915: Remove extraneous MMIO for RPS
  drm/i915: remove rps local variables
  drm/i915/bdw: Set initial rps freq to nominal
  drm/i915/bdw: Extract rp_state_caps logic
  drm/i915/bdw: RPS frequency bits are the same as HSW
  drm/i915/bdw: Implement a basic PM interrupt handler
  drm/i915/bdw: Enable RC6
  drm/i915/bdw: Ensure a context is loaded before RC6

 drivers/gpu/drm/i915/i915_debugfs.c  |  26 ++---
 drivers/gpu/drm/i915/i915_drv.h      |  31 +++--
 drivers/gpu/drm/i915/i915_gem.c      |  12 ++
 drivers/gpu/drm/i915/i915_irq.c      | 108 +++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h      |   1 +
 drivers/gpu/drm/i915/i915_sysfs.c    |  81 ++++++--------
 drivers/gpu/drm/i915/intel_display.c |   5 +
 drivers/gpu/drm/i915/intel_drv.h     |   2 +
 drivers/gpu/drm/i915/intel_pm.c      | 211 +++++++++++++++++++++--------------
 9 files changed, 308 insertions(+), 169 deletions(-)

-- 
1.8.5.5